Energy-efficient pipelined DTW architecture on hybrid embedded platforms

Zhou, Hanqing; Xu, Xiaowei; Hu, Yu; Yu, Guangyu; Yan, Zeyu; Lin, Feng; Xu, Wenyao

doi:10.1109/igcc.2015.7393707

Cited by 3 publications

(3 citation statements)

References 19 publications

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“…The core running at 100 MHz can accelerate the execution time ×40 times faster than the software counterpart. A closer comparison can be achieved with the 2D-DTW accelerator for embedded platforms [26]. As the previous accelerator, it is designed to be connected to an ARM microprocessor on a Cyclone V device from Altera, achieving a ×7.5 speed-up running at 60 MHz.…”

Section: Speed Processingmentioning

confidence: 99%

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Online Signature Verification Systems on a Low-Cost FPGA

2021

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This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The double-precision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by including a single-precision floating-point unit (FPU). The second implementation attaches a hardware accelerator to the embedded system to reduce the execution time on floating-point vectors. The last approach is a custom computing system, which is built from a large set of arithmetic circuits that replace the floating-point data with a more efficient representation based on fixed-point format. The latter system provides a very high runtime acceleration factor at the expense of using a large number of FPGA resources, a complex development cycle and no flexibility since it cannot be adapted to other biometric algorithms. By contrast, the first system provides just the opposite features, while the second approach is a mixed solution between both of them. The experimental results show that both the hardware accelerator and the custom computing system reduce the execution time by a factor ×7.6 and ×201 but increase the logic FPGA resources by a factor ×2.3 and ×5.2, respectively, in comparison with the MicroBlaze embedded system.

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Section: Speed Processingmentioning

confidence: 99%

“…The DTW accelerator [26] is much closer to the proposed version used in this paper since it implements the Euclidean distance for 2D samples. However, the resolution of samples is limited to 8-bit, and it uses the Sakoe-Chiba region.…”

Section: Speed Processingmentioning

confidence: 99%

Online Signature Verification Systems on a Low-Cost FPGA

2021

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“…This makes it very useful in applications such as gesture recognition [3], speech recognition [4], or signature recognition [5]. In the last years, special attention has been paid to computing DTW on the edge, as a way to reduce the load of communication on Internet-of-Thing (IoT) applications [6] [7] [2].…”

Section: Introductionmentioning

confidence: 99%

High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS

Hormigo-Jiménez,

Hormigo

2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is extensively used in many machine learning algorithms, especially for pattern recognition and classification. U nfortunately, i t h as a q uadratic complexity, which results in very high computational costs. Furthermore, its data dependency made it also very difficult t o parallelize. Special attention has been paid to computing DTW on the edge, as a way to reduce the load of communication on Internet-of-Thing applications. In this work, we propose a minimum area implementation of the DTW algorithm in AMD FPGAs with optimal use of the resources. That is achieved by maximizing the use time of the resources and taking advantage of the inner structure of the AMD FPGAs. This architecture could be used in small devices or as a base for a multi-core implementation with very high-throughput.

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MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers

Lin

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Energy-efficient pipelined DTW architecture on hybrid embedded platforms

Cited by 3 publications

References 19 publications

Online Signature Verification Systems on a Low-Cost FPGA

Online Signature Verification Systems on a Low-Cost FPGA

High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS

MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers

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