Energy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach

Abstract

A B S T R A C TThis paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% and 15% improvement in terms of total number of Cell counts and Area. Similarly, the proposed design structure realizes the overall power dissipation savings up to 35.3% at maximum energy dissipation of circuit, 38.6% at average energy dissipation of circuit, 36.1% at minimum energy dissipation of circuit, 36.4% at average energy dissipation of circuit and 40.1% at average switching energy dissipation compared to the latest reported designs. The power analysis and structural analysis of the proposed design is compared with its state-of-the-art counterpart designs, using QCAPro and QCADesigner 2.0.3 tools. The proposed QCA based SRAM cell design can be taken as a base design in building an ultralow power information generating systems like Microprocessors.

Novel design of cryptographic architecture of nanorouter using quantum-dot cellular automata nanotechnology

“…In contrast to the fact that the data plane uses a switch to forward data packets, the processing that takes place is determined by the packets themselves. The authors of this study have focused their attention on the design of data plane components 12 – 14 . The data plane receives information from the N incoming connections, processes it, and then sends it to the N output links.…”

Decimal to Excess-3 and Excess-3 to Decimal Code Converters in QCA Nanotechnology

“…Tile presents a combined logic function for INV and Majority gates, so the tile method is area efficient because it presents one unique block for INV and Majority gates [9]. Since reducing the occupied area, energy dissipation, and of course, improving the performance is very vital, the technology of integrated circuits was expanded [10][11][12]. In this paper by using the tile method, two code converters are presented: excess-3 code to decimal (that is the topology of 7443 IC from 74 series IC) and decimal to an excess-3 code.…”

“…Presenting seven different circuits instead of one circuit is the most important defect of this paper. Kassa et al [12] presented at first, a full adder (FA); then, with three of that FA, a binary to BCD converter was proposed. This circuit was implemented utilizing the gate method and wasn't optimized as much as possible.…”