Energy-efficient motion estimation with approximate arithmetic

Porto, Roger; Agostini, Luciano; Porto, Marcelo; Roma, Nuno; Sousa, Leonel

doi:10.1109/mmsp.2017.8122248

Cited by 16 publications

(5 citation statements)

References 19 publications

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“…Firstly, as BMO is directly related to SAD operations, we can consider archi- tectures that optimize these operators. In [19] and [20], an architectural exploration applied to SAD units is proposed to reduce energy consumption while introducing a minimum impact on the coding efficiency. Targeting at real-time processing of high definition videos, the authors in [19] present a fully combinational scheme that is able to process all the supported block sizes of current video encoders.…”

Section: Hardware Savings Estimationmentioning

confidence: 99%

“…The next levels compose an adder tree for the partial values coming from the first level. To process real-time video with 1920×1080 pixels at 60 frames per second, the authors in [19] propose an architecture with 13 SAD units (see Fig. 7).…”

Section: Hardware Savings Estimationmentioning

confidence: 99%

“…Four processing cores compose each SAD unit. The target frequency was defined to 497.66MHz, intending to process video sequences with 1920×1080 pixels at 60 frames per second [19]. The obtained SAD architecture presents a power dissipation and silicon area of 21.40mW and 179.6 gates, respectively, when synthesized for 45nm@1.1V Nangate standard cells technology [19].…”

Section: Hardware Savings Estimationmentioning

confidence: 99%

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Complexity-Aware TZS Algorithm for Mobile Video Encoders

Gonçalvès¹,

Moraes²,

Porto³

et al. 2019

JICS

Self Cite

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Video applications are significantly growing in the last years, especially in embedded/mobile systems. Modern video compression algorithms and standards, such as the High Efficiency Video Coding (HEVC), achieved a high efficiency in compression ratio. However, such efficiency has caused an augment on the complexity to encode videos. This is a serious problem especially in mobile systems, which present restrictions on processing and energy consumption. This paper presents an enhanced Test Zone Search (TZS) algorithm, aiming at complexity reduction of the Motion Estimation (ME) process in the HEVC standard and focusing efficient hardware design for mobile encoders. The proposed algorithm is composed of two strategies: an early termination scheme for TZS, called e-TZS, and the Octagonal-Axis Raster Search Pattern (OARP). When combined and implemented in the HEVC reference encoder, the strategies allowed an average complexity reduction of 75.16% in TZS, with a negligible BD-rate increase of only 0.1242% in comparison to the original algorithm. Besides, the approach presents an average block matching operation reduction of 80%, allowing hardware simplification and decreasing memory access.

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Section: Hardware Savings Estimationmentioning

confidence: 99%

Section: Hardware Savings Estimationmentioning

confidence: 99%

Section: Hardware Savings Estimationmentioning

confidence: 99%

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Complexity-Aware TZS Algorithm for Mobile Video Encoders

Gonçalvès¹,

Moraes²,

Porto³

et al. 2019

JICS

Self Cite

View full text Add to dashboard Cite

show abstract

“…Whereupon, the absolute values of the pixel differences are summed up with the SAD step. Inexact operators, in particular adders, can be applied on SAD to simplify the process, reducing the complexity and, in turn, latency (frequency) and energy consumption [47]. One alternative to regular, exact Ripple-Carry Adders (RCAs), commonly adopted in SAD, are Lower-Part-OR Adders (LOAs).…”

Section: Hardware Level Approximationmentioning

confidence: 99%

“…Porto et. al [47] studied the adoption of LOAs with different widths of the inexact portion of the operator within a hardware accelerator for motion estimation of image blocks with different sizes, up to 16x16 pixels. The hardware accelerator is strongly parallel, being able to compare the current block with 169 candidate reference blocks at a time.…”

Section: Hardware Level Approximationmentioning

confidence: 99%

Reconfigurable and approximate computing for video coding

Palumbo

2019

VLSI Architectures for Future Video Coding

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Systems perception capabilities are fundamental to make modern interconnected systems smart and, in this context, video coding is certainly a key technology. Video coding standards have been traditionally based on monolithic specifications coupled to a fixed set of profiles, capable of implementing different sub-set of functionalities of the given reference standard. Standards and profiles typically offer different features and enable different trade-offs that make them suitable for different applications and scenarios. Nevertheless, keeping the pace with constantly evolving scenarios and user's needs, for example in terms of offered quality or consumed power, is not that simple, and has led to continuous releases/updates of standards and profiles.Ideally designers should be allowed, at design-time, to select and combine coding tools and profiles to optimally match the given requirements, while guaranteeing that customized applications are still interoperable. Nevertheless, monolithic specifications tend to hide parallelism and the dataflow nature of video coding algorithms that, on the contrary, can be successfully exploited to guarantee efficient implementations and to play with different trade-offs [8].To address these issues, related to codecs design and customization, designers have been called to conceive efficient design-time methodologies

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