Energy-efficient mechanisms for managing thread context in throughput processors

Abstract

Modern graphics processing units (GPUs) use a large number of hardware threads to hide both function unit and memory access latency. Extreme multithreading requires a complicated thread scheduler as well as a large register file, which is expensive to access both in terms of energy and latency. We present two complementary techniques for reducing energy on massively-threaded processors such as GPUs. First, we examine register file caching to replace accesses to the large main register file with accesses to a smaller structure containing the immediate register working set of active threads. Second, we investigate a two-level thread scheduler that maintains a small set of active threads to hide ALU and local memory access latency and a larger set of pending threads to hide main memory latency. Combined with register file caching, a two-level thread scheduler provides a further reduction in energy by limiting the allocation of temporary register cache resources to only the currently active subset of threads. We show that on average, across a variety of real world graphics and compute workloads, a 6-entry per-thread register file cache reduces the number of reads and writes to the main register file by 50% and 59% respectively. We further show that the active thread count can be reduced by a factor of 4 with minimal impact on performance, resulting in a 36% reduction of register file energy.

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

“…It only induces 1.5% performance overhead based on our evaluation across a large set of GPGPU benchmarks (detailed experimental methodologies are described in Section 4.1. ), which also matches the observation made in [4]. During the register renaming stage, the destination register ID is renamed to a free physical register.…”

“…The output is written back to the counter, it will be read when the warp enters into the pipeline, and a larger-than-one value in the counter implies the necessity of writing to the TFET-based register. In [4], Gebhart et al found that 70% of the register values are read only once in GPGPU workloads. It implies that most TFET register values are read once, therefore, renaming the destination register to the TFET register usually causes 2-cycle extra delay: one additional cycle during the value write back, and another one when it is read by a subsequent instruction.…”

“…For example, Nvidia Fermi GPU supports more than 20,000 parallel threads and contains 2MB register files [7]. Accessing such sizeable register files leads to massive power consumption [2][3][4][5][6]. It has been reported that the register files consume 15%-20% of the GPU stream multiprocessor's power [8].…”

Warp-level divergence in GPUs: Characterization, impact, and mitigation

“…Another reason for warplevel divergence is due to warp scheduling policies which may prioritize some warps over the others in a TB. For example, the recently proposed two-level scheduling [9][17] tries to better overlap memory access latency with computations by intentionally making some warps runs somewhat faster than others. In Figure 12, we compare the impact from two scheduling policies, round robin (labeled as 'RR') and two-level (labeled as '2L').…”

Reconvergence de contrôle implicite pour les architectures SIMT

“…La politique d'ordonnancement des warps considérée consiste à sélectionner l'instruction prête la plus agée. Nous considérons une mémoire limitée en débit et de latence fixée, suivant la méthodologie observée par (Gebhart et al, 2011). Nous calibrons les paramètres du modèle d'après les résultats de microtests …”