Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations

Arya, Neelam; Soni, Teena; Pattanaik, Manisha; Sharma, Govind

doi:10.1016/j.micpro.2022.104498

Cited by 7 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, the other quotient bits are generated using LD as an approximate scheme to improve power consumption, area, and latency advantages. This paper [24] presents an energyefficient and logarithm-based approximate divider (LEAD) for ASIC and FPGA-based applications. The LEAD is based on a functional approximation of an arithmetic divider by rounding the input to the nearest power of two and calculating the division using basic addition/subtraction operations and shifters.…”

Section: Previous Workmentioning

confidence: 99%

QIAD: A quadratic interpolation approximate divider

Liu

Wang

Liu

2023

IEICE Electron. Express

View full text Add to dashboard Cite

The balance between computational performance and power consumption is a key constraint in computing systems, with integrated circuit technology posing a bottleneck. Approximate computation can trade off accuracy for performance or power improvement in error-tolerant scenarios. Division, with high computational demands and latency, is a bottleneck for computational efficiency. We propose a quadratic interpolation approximate divider (QIAD) based on multiplicative division, which has superior statistical performance. The design is simulated and synthesized at TSMC 65 nm process and tested on image color quantization, showing the best quantization effect using evaluation indicators such as PSNR, MSE, and SSIM.

show abstract

Section: Previous Workmentioning

confidence: 99%