Energy Efficiency Optimization of Task-Parallel Codes on Asymmetric Architectures

Costero, Luis; Igual, Francisco D.; Olcoz, Katzalin; Tirado, Francisco

doi:10.1109/hpcs.2017.67

Cited by 6 publications

(9 citation statements)

References 11 publications

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“…Therefore, the energy and execution time are almost the same as RWS. We observe that ERASE is able to figure out the best resource width for different DAG parallelism, specifically width 4 (2) for 𝑑𝑜𝑝=8 (16). As shown in Figure 12h, execution with lower widths (i.e.…”

Section: Evaluation On Symmetric Platformmentioning

confidence: 79%

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Chen

Manivannan

Abduljabbar

et al. 2022

ACM Trans. Archit. Code Optim.

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Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein throttling is carried out based on factors like task parallelism, stealing relations, and task criticality. This article makes the following observations: (i) leveraging DVFS on a per-task basis is impractical when using fine-grained tasking and in environments with cluster/chip-level DVFS; (ii) task moldability, wherein a single task can execute on multiple threads/cores via work-sharing, can help to reduce energy consumption; and (iii) mismatch between tasks and assigned resources (i.e., core type and number of cores) can detrimentally impact energy consumption. In this article, we propose EneRgy Aware SchedulEr (ERASE), an intra-application task scheduler on top of work stealing runtimes that aims to reduce the total energy consumption of parallel applications. It achieves energy savings by guiding scheduling decisions based on per-task energy consumption predictions of different resource configurations. In addition, ERASE is capable of adapting to both given static frequency settings and externally controlled DVFS. Overall, ERASE achieves up to 31% energy savings and improves performance by 44% on average, compared to the state-of-the-art DVFS-based schedulers.

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Section: Evaluation On Symmetric Platformmentioning

confidence: 79%

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Chen

Manivannan

Abduljabbar

et al. 2022

ACM Trans. Archit. Code Optim.

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show abstract

“…For this aforementioned reason, it is a suitable tool for collecting the necessary information for the latter software acceleration step using OmpSs. Parallelism extraction at task level using the OmpSs programming model . For this, a directed acyclic graph (DAG) is created in order to represent the task parallelism existing in the algorithm, which will allow the optimization of the computational resources. Development of techniques for energy consumption reduction and to exploit, in an efficient way, the computational resources offered by the asymmetric architectures Measurement of energy consumption in the testing environment created for the ODROID XU4 and Raspberry Pi 3 B+ boards. Experimental analysis of the attained results. …”

Section: Methods Used and Testing Environmentmentioning

confidence: 99%

“…Another type of technique for improving energy consumption corresponds to those based on the DVFS techniques, which are characterized by dynamically varying the processor's frequency and voltage at execution time in order to improve energy consumption or reduce the instant power consumed. Big.LITTLE ARM processors support frequency scaling, although only at cluster level, not at core level, so every core in a cluster will execute tasks at the same frequency …”

Section: Energy Consumption Optimizationmentioning

confidence: 99%

“…Reducing the frequency in the LITTLE cluster implies that the instantaneous power dissipated decreases. Although it is true that by reducing the frequency of the cluster, the time spent executing a task increases, this technique can be applied in those phases of parallel execution in which the execution is limited by a large number of critical tasks and a low number of non‐critical tasks; therefore, it is expected that the final impact on performance will not be high and so will the reduction in energy consumption …”

Section: Energy Consumption Optimizationmentioning

confidence: 99%

“…In this context, taking into account the scheduler provided by OmpSs, the scaling of frequencies, and the variation of the scale and step factors, a study has been carried out for the Odroid XU4 board in order to optimize the energy consumption considering different scenarios. For the experiments, only the frequency of the big cluster has been modified, because modifying the frequency of the LITTLE cluster has not a meaningful impact on the energy consumption, but a big impact on the execution time as shown in Costero et al Figures show the obtained results for different frequency values on cluster BIG (Odroid XU4 board) after processing 1200 images included in both databases (Base 450 and Base 750).…”

Section: Energy Consumption Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

Acceleration and energy consumption optimization in cascading classifiers for face detection on low‐cost ARM big. LITTLE asymmetric architectures

Corpas

Costero

Botella

et al. 2018

Circuit Theory & Apps

Self Cite

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This paper proposes a mechanism to accelerate and optimize the energy consumption of a face detection software based on Haar-like cascading classifiers, taking advantage of the features of low-cost asymmetric multicore processors (AMPs) with limited power budget. A modelling and task scheduling/allocation is proposed in order to efficiently make use of the existing features on big. LITTLE ARM processors, including (1) source-code adaptation for parallel computing, which enables code acceleration by applying the OmpSs programming model, a task-based programming model that handles data-dependencies between tasks in a transparent fashion; (2) different OmpSs task allocation policies which take into account the processor asymmetry and can dynamically set processing resources in a more efficient way based on their particular features.The proposed mechanism can be efficiently applied to take advantage of the processing elements existing on low-cost and low-energy multi-core embedded devices executing object detection algorithms based on cascading classifiers.Although these classifiers yield the best results for detection algorithms in the field of computer vision, their high computational requirements prevent them from being used on these devices under real-time requirements. Finally, we compare the energy efficiency of a heterogeneous architecture based on AMPs with a suitable task scheduling with that of a homogeneous symmetric architecture.

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Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

Bilbao

Sáez

Prieto-Matías

2023

Concurrency and Computation

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SummaryAsymmetric multicore processors (AMPs) couple high‐performance big cores and power‐efficient small ones, all exposing a shared instruction set architecture to software, but with different microarchitectural features. The energy efficiency benefits of AMPs, together with the general‐purpose nature of the various cores, have led hardware manufacturers to build commercial AMP‐based products, first for the mobile and embedded domains, and more recently, for the desktop market segment, as with the Intel Alder Lake processor family. This trend indicates that AMPs may become a solid and more energy efficient replacement for symmetric multicores in a wide range of application domains. Previous research has demonstrated that the system software can substantially improve scheduling—critical to get the most out of heterogeneous cores—by leveraging hardware facilities that are directly managed by the OS, such as performance monitoring counters, or the recently introduced Intel Thread Director technology. Unfortunately, the OS‐level support enabling access to these hardware facilities may often take a long time to be adopted in operating systems, or may come in forms that make its utilization challenging from specific levels of the system software stack, especially in production systems. To fill this gap, we propose PMCSched, an open‐source framework enabling rapid development and evaluation of custom scheduling‐related support in the Linux kernel. PMCSched greatly simplifies the design and implementation of a wide range of scheduling policies for multicore systems that operate at different system software layers without requiring to patch the kernel. To demonstrate the potential of our framework, we conduct a set of experimental case studies on asymmetry‐aware scheduling for Intel Alder Lake processors.

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Energy Efficiency Optimization of Task-Parallel Codes on Asymmetric Architectures

Cited by 6 publications

References 11 publications

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Acceleration and energy consumption optimization in cascading classifiers for face detection on low‐cost ARM big. LITTLE asymmetric architectures

Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

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