Energy Band Adjustment in a Reliable Novel Charge Plasma SiGe Source TFET to Intensify the BTBT Rate

Anvarifard, Mohammad K.; Orouji, Ali A.

doi:10.1109/ted.2021.3106891

Cited by 17 publications

(7 citation statements)

References 24 publications

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“…Due to the extremely small size of our device, we have considered the Quantum Confinement (QC) effect using the quantum momentum model (Density Gradient) [ 40 ]. Figure 20 shows the transfer characteristics with and without the use of QC at different semiconductor thicknesses.…”

Section: Resultsmentioning

confidence: 99%

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

Lin

Chang

2023

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In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at VD = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SSavg) of 30.5 mV/dec, an Ion of 3.12 × 10–5 A/μm and an Ion/Ioff ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

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Section: Resultsmentioning

confidence: 99%

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

Lin

Chang

2023

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“…The metals are chosen based on the charge plasma concept, which states that the metal for the drain can only be chosen when

φ_{D} < χ_{italicSi} + E_{g} / 2

and the metal for the source must satisfy

φ_{S} > χ_{italicSi} + E_{g} / 2

E_{g}

and

χ_{italicSi}

represent silicon's bandgap (1.1 eV) and electron affinity (4.17 eV) 29,30 . A commercially existing simulator, Silvaco ATLAS, 31 is primarily used for simulation.…”

Section: Proposed Device Structurementioning

confidence: 99%

Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement

Theja

Panchore

2023

Int J Numerical Modelling

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This paper examines a charge plasma‐based hetero‐structure full gate vertical tunnel field effect transistor (CP‐FG‐VTFET) as a dielectrically modulated biosensor. It is also compared with a charge plasma‐based short gate vertical TFET (CP‐SG‐VTFET) biosensor and a charge plasma‐based asymmetrical vertical TFET (CP‐AS‐VTFET) biosensor with identical dimensions. We examine the basic physics of these biosensors and compare their ability to recognize charged and neutral molecules. It has been noted that these designs, which use GaSb as the n‐type TFET source material, are suitable for supply voltages lower than 1.2 V. The short gate device has a lower miller capacitance and a higher drive current because it has a narrow bandgap source material. Additionally, the left and right gate alignment of asymmetrical gate architectures has a considerable impact on the sensitivity of the device. Therefore, a simulation is conducted to assess the effects of gate misalignment on biosensor surface potential and drain current sensitivity. In addition, various figures of merits (FOMs) are computed for the device utilizing the dielectric constant range of 1–12, including linearity, sensitivity, and evaluation of noise characteristics. The widely available Silvaco TCAD was employed to simulate the proposed VTFET biosensors. A comprehensive evaluation of the FOM values showed that the CP‐FG‐VTFET is a promising device in terms of linearity and sensitivity.

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“…Our simulations using Sentaurus TCAD [ 29 ], which include models for Shockley–Read–Hall recombination, bandgap narrowing, doping dependence, nonlocal band-to-band tunneling, high-field dependence of mobility, trap-assisted tunneling. Due to the thin channel thickness, it is necessary to consider the quantum confinement effect [ 30 ]. To ensure the accuracy and feasibility of our simulations, we have calibrated our simulation model using an actual fabricated TFET [ 31 ], as shown in Fig.…”

Section: Device Structure and Operating Mechanismmentioning

confidence: 99%

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

Lin,

Cheng

2023

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In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 $$\times$$ × 10–6 A/μm, and the ION/IOFF ratio is 1.34 $$\times$$ × 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

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Energy Band Adjustment in a Reliable Novel Charge Plasma SiGe Source TFET to Intensify the BTBT Rate

Cited by 17 publications

References 24 publications

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

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