Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache

Chen, Xunchao; Khoshavi, Navid; DeMara, Ronald F.; Wang, Jim; Huang, Dan; Wen, Wujie; Chen, Yiran

doi:10.1109/tc.2016.2625245

Cited by 39 publications

(7 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These techniques can decrease STT-MRAM energy consumption by 17 percent, while increasing instructions per cycle (IPC) by 9 percent across the PARSEC benchmark suite. 2 Utilization of NVM also introduces new challenges to file structures and OSs, such as facilitating the storage, migration, and management of long-lifetime data throughout the memory hierarchy. Memory policies, data structures, and file systems capable of leveraging NVM continue to advance.…”

Section: Editor Ron Vettermentioning

confidence: 99%

Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack

DeMara

Montuschi

2018

Computer

Self Cite

View full text Add to dashboard Cite

Section: Editor Ron Vettermentioning

confidence: 99%

Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack

DeMara

Montuschi

2018

Computer

Self Cite

View full text Add to dashboard Cite

“…In CNN training, the number of memory read accesses is much higher than the writes. As MLC STT-RAM is reported as having promising single-step read performance and energy consumption [9,11,13,16], using this emerging memory technology offers opportunity of improving the overall performance of CNN training. Issues and opportunities with MLC STT-RAM cell.…”

Section: Motivationmentioning

confidence: 99%

“…Our evaluation adopts the MLC STT-RAM cell performance, energy, and area parameters provided by prior MLC STT-RAM designs [9,11,16]. We scale the parameters to 32nm technology node the same way as previous studies [13].…”

Section: Performance and Energy Modelingmentioning

confidence: 99%

Leveraging MLC STT-RAM for energy-efficient CNN training

Zhao

2018

Proceedings of the International Symposium on Memory Systems

View full text Add to dashboard Cite

Graphics Processing Units (GPUs) are extensively used in training of convolutional neural networks (CNNs) due to their promising compute capability. However, GPU memory capacity, bandwidth, and energy are becoming critical system bottlenecks with increasingly larger and deeper training models. This paper proposes an energy-efficient GPU memory management scheme by employing MLC STT-RAM as GPU memory to accommodate the image classification training workloads. We propose a data remapping scheme that exploits the asymmetry access latency and energy across soft and hard bits in MLC STT-RAM cells and the memory access characteristics in image classification training workloads. Furthermore, our design enables (i) energy-efficient memory access by leveraging bit-level similarity in training data and (ii) optimal feature map encoding to compress the contiguous 0s in feature maps. Our design reduces VGG-19 and AlexNet training time, GPU memory access energy and capacity utilization by 76% and 70%, 45% and 40%, 26.9% and 26%, respectively.

show abstract

“…Such complex resistance state transition and detection processes for write and read operations, respectively, seriously degrade performance, power consumption, and endurance. Previous works have mitigated the degradation of multi-level cell (MLC) STT-MRAMs [12,17,18,19,20,21,22,23,24,25,26,27], but they are not effective for a large LLC comprised of series TLC STT-MRAMs. In this paper, we propose the architecture and operation of a novel LLC comprised of series TLC STT-MRAMs.…”

Section: Introductionmentioning

confidence: 99%

TLC STT-MRAM aware LLC for multicore processor

Park

Hur

Jang

2020

IEICE Electron. Express

View full text Add to dashboard Cite

Since state-of-the-art multicore processors that execute complicated applications demand a large last-level cache (LLC) for reducing memory latency, next-generation memories have being recently attracted great attentions. Triple-level cell (TLC) spin-transfer torque (STT)-magnetic random access memories (MRAMs) provide high storage density, but degrade latency and power consumption due to three-step resistance state transition and detection processes for write and read operations, respectively. In this paper, we propose a TLC STT-MRAMs aware LLC that limit such penalties for multicore processors. Our LLC minimizes the occurrence of three-step resistance state transition and detection processes via the proposed cell division mapping and conditional block swapping techniques. Experimental results show that the proposed LLC achieves on average 17.2% higher performance and 17.9% lower power consumption than conventional LLCs comprised of TLC STT-MRAMs.

show abstract

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache

Cited by 39 publications

References 35 publications

Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack

Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack

Leveraging MLC STT-RAM for energy-efficient CNN training

TLC STT-MRAM aware LLC for multicore processor

Contact Info

Product

Resources

About