Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices

Chakma, Gangotree; Nicholas, Skuda,; Schuman, Catherine D.; Plank, James S.; Dean, Mark E.; Rose, Garrett S.

doi:10.1145/3194554.3194611

Cited by 11 publications

(7 citation statements)

References 9 publications

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“…The neuromorphic non von Neumann architectures discussed in Section IV are considered to be a promising solution for energy-related issues and optimization of such systems. Moreover, neuromorphic architectures can be used to solve the cloud computing energyrelated issues in memory and processing units and to achieve energy-efficient computing [30].…”

Section: Edge Devices and Emerging Neural Computingmentioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

Krestinskaya

James

Chua

2020

IEEE Trans. Neural Netw. Learning Syst.

219

120

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The volume, veracity, variability and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing.

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Section: Edge Devices and Emerging Neural Computingmentioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

Krestinskaya

James

Chua

2020

IEEE Trans. Neural Netw. Learning Syst.

219

120

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“…Hence, the search for materials to realize low-power electronics is a pressing need, not only for AI-related tasks but also for the development of other power-constrained devices such as drug-delivery systems, and imaging and sensing devices . Neuromorphic architectures, whose structure and functions are inspired by the neural networks in the brain, are a promising platform to realize low-power electronics and thus maximize the energy and computing efficiency of AI tasks. , Previous studies have shown that neuromorphic architectures can in principle operate with orders of magnitude less power than traditional computing systems, , due to their massively parallel and event-driven nature .…”

Section: Introductionmentioning

confidence: 99%

Metallic Interface between Two Insulating Phases of La_1–xSr_xCoO_3−δ

Zhang,

Galli

2024

Chem. Mater.

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Metal−insulator transitions occurring in several transition metal oxides (TMOs) can be used to realize energy-efficient resistive switching devices, which in turn can be utilized as basic components of neuromorphic architectures. Using first-principles calculations, we predict the occurrence of an insulator-to-metal transition at the interface of two insulators, the perovskite (P) and brownmillerite (BM) phases of promising TMOs for neuromorphic applications, LaSrCoO 3−δ . The electronic structure of the interface can be engineered by controlling strain, Sr content, and oxygen vacancy concentration. A metallic interface arises from the combined effect of structural distortions and charge transfer between the BM and P phases, which leads to interfacial orbital reconstruction. Our results point to the possibility of realizing energy-efficient resistive switching states at a two-dimensional interface within the same TMO solid, thus opening new routes for the design of lowpower neuromorphic devices.

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“…This enables parallel update of the synaptic weights of the crossbar array, and training of the crossbar array becomes efficient. In edge computing/edge artificial intelligence (AI), enabling on-chip learning at the edge devices prevents data breach, which can otherwise happen if edge devices only have inference facility [6][7][8]. Since on-chip learning in crossbar array is very efficient due to efficient VMM and outer product operations in it, on-chip learning in crossbar arrays becomes very attractive for edge AI applications [4,6].…”

Section: Introduction 1motivationmentioning

confidence: 99%

Impact of edge defects on the synaptic characteristic of a ferromagnetic domain-wall device and on on-chip learning

Singh Yadav,

Sadashiva,

Holla

et al. 2023

Neuromorph. Comput. Eng.

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Topological-soliton-based devices, like the ferromagnetic domain-wall device, have been proposed as non-volatile memory (NVM) synapses in electronic crossbar arrays for fast and energy-efficient implementation of on-chip learning of neural networks. High linearity and symmetry in the synaptic weight-update characteristic of the device (long-term potentiation (LTP) and long-term depression (LTD)) are important requirements to obtain high classification/ regression accuracy in such an on-chip learning scheme. However, obtaining such linear and symmetric LTP and LTD characteristics in the ferromagnetic domain-wall device has remained a challenge. Here, we first carry out micromagnetic simulations of the device to show that the incorporation of defects at the edges of the device, with the defects having higher perpendicular magnetic anisotropy (PMA) compared to the rest of the ferromagnetic layer, leads to massive improvement in the linearity and symmetry of the LTP and LTD characteristics of the device. This is because these defects act as pinning centres for the domain wall and prevent it from moving during the delay time between two consecutive programming current pulses, which is not the case when the device doesn't have defects. Next, we carry out system-level simulations of two crossbar arrays with synaptic characteristics of domain-wall synapse devices incorporated in them: one without such defects, and one with such defects. For on-chip learning of both Long Short Term Memory Networks (LSTMs) (using a regression task) and Fully Connected Neural Networks (FCNN) (using a classification task), we show improved performance when the domain-wall synapse devices have defects at the edges. We also estimate the energy consumption in these synaptic devices and project their scaling, with respect to on-chip learning in corresponding crossbar arrays.

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Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices

Cited by 11 publications

References 9 publications

Neuromemristive Circuits for Edge Computing: A Review

Neuromemristive Circuits for Edge Computing: A Review

Metallic Interface between Two Insulating Phases of La_1–xSr_xCoO_3−δ

Impact of edge defects on the synaptic characteristic of a ferromagnetic domain-wall device and on on-chip learning

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Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices

Cited by 11 publications

References 9 publications

Neuromemristive Circuits for Edge Computing: A Review

Neuromemristive Circuits for Edge Computing: A Review

Metallic Interface between Two Insulating Phases of La1–xSrxCoO3−δ

Impact of edge defects on the synaptic characteristic of a ferromagnetic domain-wall device and on on-chip learning

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Product

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Metallic Interface between Two Insulating Phases of La_1–xSr_xCoO_3−δ