End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Obermaisser, Roman; Owda, Zaher; Abuteir, Mohammed; Ahmadian, Hamidreza; Weber, Donatus

doi:10.1109/dsd.2014.34

Cited by 14 publications

(7 citation statements)

References 16 publications

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“…Obermaisser et al [20] described the mixed-criticality systems for end to end real-time communication, which involves gateways between multiple off-chip networks, Gateway between off-chip and on-chip networks. The gateway node resolving the contention between source controlled and autonomous networks and also supports end-to-end addressing and routing.…”

Section: Related Workmentioning

confidence: 99%

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Guruprasad¹,

B.S²

2019

IJACSA

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Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestionfree adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

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Section: Related Workmentioning

confidence: 99%

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Guruprasad¹,

B.S²

2019

IJACSA

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“…We refer readers to the general survey on CPS [37] for more information. There are many similar/relevant completed (such as CONTREX [10] , MultiPARTES [13] , ASAM [38] , SCUBA [39] ) and on-going European projects (such as DREAMS [11] , EM C 2 [12] ) which are focused on many different aspects (mostly focused on the mixed-criticality application domain) of CPS. We are discussing few of them which are more relevant to our works.…”

Section: Related Workmentioning

confidence: 99%

“…The AXIOM project (Agile, eXtensible, fast I/O Module) provides a general framework focusing on easily mapping applications to multi-board processing platforms [8,9] . Unlike other research effort s (such as CONTREX [10] , DREAMS [11] , EM C 2 [12] , MultiPARTES [13] ) that focus mainly on the mixed-criticality appli- cations, AXIOM provides a generic platform with its complete application development suite. Despite the existence of many FPGAbased boards, to the best of our knowledge our approach is the first that combines all the features (especially parallel programmability, connectivity and scalability).…”

Section: Introductionmentioning

confidence: 99%

The AXIOM platform for next-generation cyber physical systems

Theodoropoulos

Mazumdar

Ayguadé

et al. 2017

Microprocessors and Microsystems

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Cyber-Physical Systems (CPSs) are widely used in many applications that require interactions between humans and their physical environment. These systems usually integrate a set of hardware-software components for optimal application execution in terms of performance and energy consumption. The AXIOM project (Agile, eXtensible, fast I/O Module), presented in this paper, proposes a hardware-software platform for CPS coupled with an easy parallel programming model and sufficient connectivity so that the performance can scale-up by adding multiple boards. AXIOM supports a task-based programming model based on OmpSs and leverages a high-speed, inexpensive communication interface called AXIOM-Link. The board also tightly couples the CPU with reconfigurable resources to accelerate portions of the applications. As case studies, AXIOM uses smart video surveillance, and smart home living applicationsThis work is partially supported by the European Union H2020 program through the AXIOM project (grant ICT-01-2014 GA\ud 645496) and HiPEAC (GA 687698), by the Spanish Government through Programa Severo Ochoa (SEV-2015-0493), by the Spanish Ministry of Science and Technology through TIN2015-65316-P project, and by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272). We also thank the Xilinx University Program for its hardware and software donations.Peer ReviewedPostprint (author's final draft

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“…A Worst-Case Latency Delay (WCLD) (line 11 to 14) is computed based on the formula in [23] to determine the contribution to the critical path. if the traffic type is TT then 7: for each hop do 8: reserve transmission time in network channel 9: end for 10: else 11: for each hop do 12: reserve bandwidth for transmission in network channel 13: Compute WCLD 14: end for 15: end if 16: if target service received all messages from relied upon services then In case all inputs for the target service have been scheduled, the target service will change its status to active and set T EP S equal to the message reception time.…”

Section: Scheduling Modelmentioning

confidence: 99%

Scheduling of rate-constrained and time-triggered traffic in multi-cluster TTEthernet systems

Abuteir

Obermaisser

2015

2015 IEEE 13th International Conference on Industrial Informatics (INDIN)

Self Cite

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Multi-cluster systems with real-time networks are gaining increasing importance to address the communication needs of large-scale embedded systems in different domains such as automotive, factory automation and health-care systems. At the same time, heterogeneous application subsystems with varying criticality levels require different timing models including time-triggered communication, event-triggered communication with rate-constraints and best-effort communication. An example is the coexistence of periodic control functions, event-triggered comfort functions and streaming multimedia services of in-vehicle electronic systems. This paper presents a scheduling algorithm as well as a simulation and verification framework for such multi-cluster systems. We support the allocation and scheduling of time-triggered and rate-constrained services to processing elements and communication links of multiple Time-Triggered Ethernet (TTE) clusters. The simulation and verification framework supports the automatic generation of test cases based on generic scenario parameters including the connectivity degree as well as the number of clusters, processing elements, switches and services. Thereby, we enable a comprehensive evaluation of the scheduling algorithm for use cases of varying complexity. In addition, the simulation and verification framework is a foundation for the systematic comparison of different scheduling algorithms including the evaluation of schedulability and runtime for different types of scenarios. 1

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End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Cited by 14 publications

References 16 publications

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

The AXIOM platform for next-generation cyber physical systems

Scheduling of rate-constrained and time-triggered traffic in multi-cluster TTEthernet systems

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