Encircle routing: An efficient deterministic network on chip routing algorithm

Umapathy, Shylesh; Shah, Meet K.; Wang, Nan

doi:10.1109/ccwc.2018.8301661

Cited by 3 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another study found that this algorithm helps in the redistribution of traffic, which enhances the system's performance level and reduces congestion at the central. The encircle routing algorithm was presented in another article [92]. This algorithm, by the redistribution of traffic, helps enhance system performance and reduce congestion at the centre hub of the network.…”

Section: Workload Distributionmentioning

confidence: 99%

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Muhsen,

Azura Husin,

Binti Zolkepli

et al. 2024

Iraqi Journal For Computer Science and Mathematics

View full text Add to dashboard Cite

Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data from credible resources, including IEEE Xplore ®, ScienceDirect, Association for Computing Machinery and Web of Science. Out of the 906 research papers reviewed, only 51 were considered relevant to the investigation on NoC RTs. The study addresses issues related to NoC routing and suggests new approaches for in-package data negotiating. In addition, it gives an overview of the recent research on routing strategies and numerous algorithms that can be used for NoC-based MPSoCs. The literature analysis addresses current obstacles and delineates potential future avenues, recommendations, and challenges analyzing techniques to assess performance utilizing metrics within the TCCM framework.

show abstract

Section: Workload Distributionmentioning

confidence: 99%

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Muhsen,

Azura Husin,

Binti Zolkepli

et al. 2024

Iraqi Journal For Computer Science and Mathematics

View full text Add to dashboard Cite

show abstract

“…In ZigZag, packets forwarded along the axis have a greater distance, and when the difference along both axes remains only one hop, it starts forwarding in the ZigZag way. Some modifications to XY algorithms are also present by Atik et al [12] and Umapathy et al [112]. In [12] they implement buffer allocation on-demand basis, and [112] proposed to Encircle routing where the network is partitioned into regions, and then packets are forwarded in such a way that they do not enter another region.…”

Section: A Workload Distributionmentioning

confidence: 99%

“…Some modifications to XY algorithms are also present by Atik et al [12] and Umapathy et al [112]. In [12] they implement buffer allocation on-demand basis, and [112] proposed to Encircle routing where the network is partitioned into regions, and then packets are forwarded in such a way that they do not enter another region. Some research work also considers core lifetime.…”

Section: A Workload Distributionmentioning

confidence: 99%

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

View full text Add to dashboard Cite

Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

show abstract

A high-level simulator for Network-on-Chip

Paris,

Pedrino

2024

ICA

View full text Add to dashboard Cite

This study presents a high-level simulator for Network-on-Chip (NoC), designed for many-core architectures, and integrated with the PlatEMO platform. The motivation for developing this tool arose from the need to evaluate the behavior of application mapping algorithms and the routing, both aspects are essential in the implementation and design of NoC architectures. This analysis underscored the importance of having effective NoC simulators as tools that allow for studying and comparing various network technologies while ensuring a controlled simulation environment. During this investigation and evaluation, some simulators, such as Noxim, NoCTweak, and NoCmap, among others, offered configurable parameters for application traffic, options to synthetically define topology and packet traffic patterns. Additionally, they include mapping options that optimize latency and energy consumption, routing algorithms, technological settings such as the CMOS process, and measurement options for evaluating performance metrics such as throughput and power usage. However, while these simulators meet detailed technical demands, they are mostly restricted to analyzing the low-level elements of the architecture, thus hindering quick and easy under- standing for non-specialists. This insight underscored the challenge in developing a tool that balances detailed analysis with a comprehensive learning perspective, considering the specific restrictions of each simulator analyzed. Experiments demonstrated the proposed simulator efficacy in handling algorithms like GA, PSO, and SA variant, and, surprisingly, revealed limitations of the XY algorithm in Mesh topologies, indicating the need for further investigation to confirm these findings. Future work will expand the simulator functionalities, incorporating a broader range of algorithms and performance metrics, to establish it as an indispensable tool for research and development in NoCs.

show abstract

Encircle routing: An efficient deterministic network on chip routing algorithm

Cited by 3 publications

References 7 publications

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

A high-level simulator for Network-on-Chip

Contact Info

Product

Resources

About