Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility

Dhanuskodi, Siva Nishok; Holcomb, Daniel

doi:10.1109/isvlsi.2019.00064

Cited by 6 publications

(3 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some examples include randomly multiplexing two different S-Boxes [18], adjusting processvoltage-temperature (PVT) parameters (e.g. via Dynamic Voltage Frequency Scaling -DVFS) [19], injecting noises [20], controlling the flow of data [21], etc. On the other hand, the Fig.…”

Section: A Sca Hiding Countermeasuresmentioning

confidence: 99%

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Chong

Chen

et al. 2021

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delayline control and a data-propagation control to amplify the dualhiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronouslogic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs.

show abstract

Section: A Sca Hiding Countermeasuresmentioning

confidence: 99%

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Chong

Chen

et al. 2021

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Horizontal-hiding increases the SCA resistance of the cryptographic devices by randomizing the execution of the cryptographic operations, as SCA requires the PLIs to be highly aligned to perform key extraction effectively. Various horizontal-hiding countermeasures had been reported since the discovery of SCA, including state-shift clock [14], random shuffling of operations [39], Globally Asynchronous Locally Synchronous (GALS) [15] design, and asynchronous-logic (async-logic) design [16]. Async-logic designs are self-timed circuits that do not rely on a global clock signal to control the circuits' operations.…”

Section: Horizontal-hidingmentioning

confidence: 99%

“…controlling the data flow [39], and so on. On the contrary, uniformization seeks to obscure adversaries by generating analogous leakage patterns from one encryption to the next.…”

Section: A Sca Hiding Countermeasuresmentioning

confidence: 99%

Secured asynchronous-logic cryptography circuits to countermeasure against side-channel attack

View full text Add to dashboard Cite

 I contributed to the manuscript drafting, improved the design of asynchronous-logic AES, and implemented the asynchronouslogic AES on FPGAs  Chen Juncheng and Nay Aung Kyaw assisted in conducting SCA evaluations of the asynchronous-logic AES.  Ne Kyaw Zwa Lwin and I prepared the necessary library cells for FPGA implementation of the asynchronous-logic AES.  Dr. Ho Weng Geng assisted in designing the architecture of asynchronous-logic AES.  Prof. Joseph Chang offered guidance on the implementation of asynchronous-logic designs.  Prof. Gwee Bah Hwee provided the initial project direction and edited the manuscript drafts. iv 2.

show abstract

VLSI Implementation of Triple-DES Block Cipher

Subaselvi¹,

Mytheesh²,

Sanjay³

et al. 2023

2023 7th International Conference on Computing Methodologies and Communication (ICCMC)

View full text Add to dashboard Cite

Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility

Cited by 6 publications

References 17 publications

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Secured asynchronous-logic cryptography circuits to countermeasure against side-channel attack

VLSI Implementation of Triple-DES Block Cipher

Contact Info

Product

Resources

About