Enabling accurate power profiling of HPC applications on exascale systems

Abstract

Despite being one of the most important limiting factors on the road to exascale computing, power is not yet considered a "first-class citizen" among the system resources. As a result, there is no clear OS interface that exposes accurate resource power consumption to user-level runtimes that implement power-aware software algorithms.In this work we propose a System Monitor Interface (SMI) between the OS and the user runtime that exposes accurate, per-core power consumption. To make up for the lack of reliable per-core power sensors, we implement a proxy power sensor, based on a regression analysis of core activity, that provides per-core information. SMI effectively hides the implementation details from the user, who has the perception of reading power information from a real sensor. This allows us these proxy sensors to be replaced with real hardware sensors when the latter becomes available, without the need to modify user-level software.Using SMI and the proxy power sensors, we implement a power profiling runtime library and analyzed applications from the NPB benchmark suite and the Exascale Co-Design Centers. Our results show that accurate, per-core power information is necessary for the development of exascale system software and for comprehensively understanding the power characteristics of parallel scientific applications.

Modeling CPU Energy Consumption of HPC Applications on the IBM POWER7

“…Although using micro-benchmarks is a popular method in related work to train power and energy models [6], it often requires tuning such benchmarks to specific hardware characteristics. Considering the complexity of today's processors, including multi-threading and available execution paths, this introduces additional effort and possible causes for inaccuracy.…”

“…Kestor et al [6] developed a per-core power model for an AMD Interlagos system and suggest the use of a System Management Interface (SMI) to enable easy access to power sensor values, whether they are measured or modeled. Similarly, Goel et al built models [7] for different Intel and AMD platforms.…”

“…Since the POWER7 offers over 500 different hardware counter events [24], a smaller subset must be derived. One approach in related work is to first manually select a medium number of hardware counters that seems like a good fit with regard to the hardware architecture [6]. We also employ this method of initial counter selection.…”

“…We also employ this method of initial counter selection. However, in [6] a series of benchmarks is run afterwards and the number of counters further reduced by computing correlation coefficients between the counters themselves, as well as correlation coefficients between counters and measured energy values. While this approach leads to models with acceptable accuracy, we found that empirically selecting a different (but mostly not disjoint) set of counters yields better results.…”

Measuring and modeling on-chip interconnect power on real hardware

“…Component-level modeling using performance counters: Regression-based power models constructed using performance counters have the potential to estimate the power consumption of several components within a processor. Several works [30], [4], [9], [17], [37] have provided a breakdown for many components within a processor. However, these power models were only validated for overall power consumption and cannot be relied upon for component-level estimation.…”