Enabling a Uniform Programming Model Across the Software/Hardware Boundary

Abstract

In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single pthreads multithreaded application program and compiled to run on the CPU or synthesized to run on the FPGA. The hthreads system, in general, is unique within the reconfigurable computing community as it abstracts the CPU/FPGA components into a unified custom threaded multiprocessor architecture platform. To support the abstraction of the CPU/FPGA component boundary, we have created the hardware thread interface (HWTI) component that frees the designer from having to specify and embed platform specific instructions to form customized hardware/software interactions. Instead, the hardware thread interface supports the generalized pthreads API semantics, and allows passing of abstract data types between hardware and software threads. Thus the hardware thread interface provides an abstract, platform independent compilation target that enables thread and instruction-level parallelism across the software/hardware boundary.

Supporting High Level Language Semantics within Hardware Resident Threads

“…Pointers and a function call stack are often two capabilities left out. Support for pointers have largely been solved by translating a pointer address into a bus operation [9,2]. Both the HWTI and Altera's C2H uses this method to support pointers.…”

“…Initially the HWTI was designed to abstract the hardware / software interface by providing the same communication and synchronization services available to software threads to independent and concurrently executing hardware threads. The details of this initial work are described in [2]. However, once we started developing our own C to HDL tool it became clear that the HWTI needed to be improved to provide a generalized function call model with equivalent HLL runtime services.…”

Automatic Reconfigurable System-on-Chip design with run-time hardware/software partitioning

“…Migration and switching of hardware/software process (thread) is implemented by modifying operating system to support hardware process (thread). So this method is called process-level (thread-level) hardware/software partitioning [10][11][12][13].…”

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

“…Some authors [14], for example, have proposed a hardware-centric parallel programming model targeting mainly the design of networking applications. Other authors [15], [16], in a work closer to ours, have investigated system support for multithreaded reconfigurable applications; however, they concentrate on efficient implementation in hardware of thread synchronisation primitives and rapid scheduling support. On our side, we concentrate on the unified memory space and seamless integration of SW and HW, thus the two approaches are complementary.…”