Empirical studies of competitve spinning for a shared-memory multiprocessor

Karlin, Anna R.; Li, Kai; Manasse, Mark S.; Owicki, Susan

doi:10.1145/121132.286599

Cited by 107 publications

(65 citation statements)

References 11 publications

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“…MCS-NB and CLH-NB are abortable queue-based locks with non-blocking timeout [27]. We also test spinthen-yield variants [13] of each lock in which threads yield the processors after exceeding a wait threshold. Finally, we test preemption-safe locks dependent on scheduling control APIs: CLH-CSP, TAS-CSP, Handshaking, CLH-PM, and SmartQ.…”

Section: Microbenchmark Resultsmentioning

confidence: 99%

“…One might expect a spin-then-yield policy [13] to allow other locks to match TP locks in preemption adaptivity. In Figure 9 we test this hypothesis with a 50 µs spinning time threshold and a 2 cache line critical section.…”

Section: Comparison To User-level Locksmentioning

confidence: 99%

“…Unfortunately, this solution comes with hidden drawbacks: queue-based locks are highly vulnerable to preemption, but test-and-set locks do not scale beyond a modest number of processors. Although several heuristic strategies can reduce wasted spinning time [13,16], multiprogrammed systems usually rely on non-queue-based locks [20]. Our goal is to combine the efficiency and scalability of queue-based spin locks with the preemption tolerance of the scheduler-based approach.…”

Section: Introductionmentioning

confidence: 99%

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Preemption Adaptivity in Time-Published Queue-Based Spin Locks

Scherer

Scott

2005

Lecture Notes in Computer Science

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The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based locks incur the overhead of a full context switch between threads and are thus unacceptably slow for many applications. Spin locks offer low overhead, but they either scale poorly on large-scale SMPs (test-and-set style locks) or behave poorly in the presence of preemption (queue-based locks).Previous work has shown how to build preemption-tolerant locks using an extended kernel interface, but such locks are neither portable to nor even compatible with most operating systems.In this work, we propose a time-publishing heuristic in which each thread periodically records its current timestamp to a shared memory location. Given the high resolution, roughly synchronized clocks of modern processors, this convention allows threads to guess accurately which peers are active based on the currency of their timestamps. We implement two queuebased locks, MCS-TP and CLH-TP, and evaluate their performance relative to both traditional spin locks and preemption-safe locks on a 32-processor IBM p690 multiprocessor. Experimental results indicate that time-published locks make it feasible, for the first time, to use queue-based spin locks on multiprogrammed systems with a standard kernel interface.

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Section: Microbenchmark Resultsmentioning

confidence: 99%

Section: Comparison To User-level Locksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Preemption Adaptivity in Time-Published Queue-Based Spin Locks

Scherer

Scott

2005

Lecture Notes in Computer Science

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“…The three events that trigger page migrations require at most as many page migrations as the size of the memory affinity set of a thread which is migrated, preempted, or resumed. Clearly, if the thread that claims a page keeps executing on node k for less than t mas , there is no time to amortize the cost of migrating the pages to k. If the thread keeps executing on k for more than t mas , the pages will move to k in time to reduce some of the latency of memory accesses issued by processors in k. 6 Since the algorithm does not know in advance how long each thread will keep running on the same node, it chooses to competitively wait for t thr before migrating pages to k [13].…”

Section: Page Migration Criterionmentioning

confidence: 99%

Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors

Nikolopoulos

Polychronopoulos

Papatheodorou

et al. 2002

Journal of Parallel and Distributed Computing

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The performance of multiprogrammed shared-memory multiprocessors suffers often from scheduler interventions that neglect data locality. On cachecoherent distributed shared-memory (DSM) multiprocessors, such scheduler interventions tend to increase the rate of remote memory accesses. This paper presents a novel dynamic page migration algorithm that remedies this problem in iterative parallel programs. The purpose of the algorithm is the early detection of pages that will most likely be accessed remotely by threads associated with them via a thread-to-memory affinity relation. The key mechanism that enables timely identification of these pages is a communication interface between the page migration engine and the operating system scheduler. The algorithm improves previously proposed competitive page migration algorithms in many aspects, including accuracy, timeliness and cost amortization. Most notably, the algorithm is not biased by obsolete memory access history that may be accumulated in the page access counters at runtime. Experiments on the SGI Origin2000 show that the algorithm outperforms by far the best static page placement algorithm and a customized page migration engine implemented in IRIX, the Origin2000 operating system. The algorithm is implemented at user-level and its functionality is orthogonal to the scheduling policy of the operating system. # 2002 Elsevier Science (USA)

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“…On a failed synchronization, the trap handler is responsible for implementing the waiting algorithm that decides whether to poll or to block the thread. Karlin et al 11 and Lim and Agarwal 14 i n vestigate the performance of various waiting algorithms. They show polling for some length of time before blocking can lead to better performance, and investigate various methods for determining how long to poll before blocking.…”

Section: Handling Failed Synchronizations In Softwarementioning

confidence: 99%

Low-Cost Support for Fine-Grain Synchronization in Multiprocessors

Kranz

Lim

Agarwal

1994

The Kluwer International Series in Engineering and Computer Science

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As multiprocessors scale beyond the limits of a few tens of processors, they must look beyond traditional methods of synchronization to minimize serialization and achieve the high degrees of parallelism required to utilize large machines. By allowing synchronization at the level of the smallest unit of memory, ne-grain synchronization achieves these goals. Unfortunately, supporting e cient ne-grain synchronization without inordinate amounts of hardware has remained a challenge. This paper describes the support for ne-grain synchronization provided by the Alewife system. The premise underlying Alewife's implementation is that successful synchronization attempts are the common case when serialization is minimized through word-level synchronization. For our applications, the failure rates were less than 7 . E ciency at low hardware cost is achieved by providing hardware support to streamline successful synchronization attempts and relegating other non-critical operations to software. Alewife provides a large synchronization name space by associating full empty bits with each memory word. Successful synchronization attempts execute at normal load-store speeds, while attempts that fail invoke appropriate software trap handlers through a fast trap mechanism. The software handlers deal with the issues of retrying versus blocking, queueing, and rescheduling. The e ciency of Alewife's mechanisms is analyzed by comparing the costs of various synchronization operations and parallel application execution time. In several applications we studied, our hardware support improved performance by 35 50 .

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Empirical studies of competitve spinning for a shared-memory multiprocessor

Cited by 107 publications

References 11 publications

Preemption Adaptivity in Time-Published Queue-Based Spin Locks

Preemption Adaptivity in Time-Published Queue-Based Spin Locks

Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors

Low-Cost Support for Fine-Grain Synchronization in Multiprocessors

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