EMI Effects in CMOS Time-Mode Circuits

Richelli, Anna; Colalongo, L.; Kovács-Vajna, Zsolt Miklós

doi:10.1109/emceurope48519.2020.9245751

Cited by 1 publication

(2 citation statements)

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“…It has recently been demonstrated that the effect of the electromagnetic interferences can affect a generic VCDU as well as the voltage-to-time converter (VTC) based on VCDU [13,14]. The interferences can indeed reach the devices through the I/O pins and they can eventually lead to failures [10][11][12] in a generic-integrated circuit; in the case of time-mode circuits, the interfering signal can cause, in particular, an EMI-induced jitter, as illustrated in Figure 15.…”

Section: Emimentioning

confidence: 99%

“…The latter can indeed be susceptible to interferences. In particular, in the voltage-controlled delay unit, the effect of interferences is a strong variation of the delay, which can be named EMI-induced jitter [13,14]. In this paper, a voltage-controlled delay unit is proposed, with a rail-to-rail linearity range and reduced jitter caused by the electromagnetic interferences' EMI.…”

Section: Introductionmentioning

confidence: 99%

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Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter

2022

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This paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay.

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