Emerging on-ship debugging techniques for real-time embedded systems

MacNamee, Ciaran; Heffernan, Donal

doi:10.1049/cce:20000608

Cited by 39 publications

(12 citation statements)

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“…Standard ports (RS232, JTAG) are commonly used for the physical connection [19,20], but their capabilities vary widely. Several standardization efforts for OCD infrastructures and interfaces were initiated on recent years [21][22][23].…”

Section: Fault Injection Via Ocdmentioning

confidence: 99%

Real-time fault injection using enhanced on-chip debug infrastructures

Fidalgo

Gericota

Alves

et al. 2011

Microprocessors and Microsystems

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The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and some-times real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on -chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in micro-processor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off -The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concern ing performance gain and silicon overhead.

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Section: Fault Injection Via Ocdmentioning

confidence: 99%

Real-time fault injection using enhanced on-chip debug infrastructures

Fidalgo

Gericota

Alves

et al. 2011

Microprocessors and Microsystems

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“…A complementary approach to scan is to monitor only a subset of internal signals that are dumped in real-time in a trace buffer. While scan-based debug concepts have emerged from the manufacturing test research, trace bufferbased debug, which is discussed next, has been influenced by software debugging used in embedded systems [16].…”

Section: Prior Workmentioning

confidence: 99%

“…On the one hand, for the special-purpose case (e.g., [8]) the compression solutions are well established [10,16]. The key idea for width compression is to probe a subset of signals from which the state of the embedded processor can be reconstructed as accurately as possible (e.g., pipeline status signals or indirect branch signals).…”

Section: Motivation and Objectivementioning

confidence: 99%

Low Cost Debug Architecture using Lossy Compression for Silicon Debug

Anis

Nicolici

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…The third phase compresses the trace by finding the similarity of nearby data segments in the trace. By combining these three phases, our hardware is capable of real-time compression and achieving compression ratio of 100:1, far better than 5:1 achieved by typical existing approaches [6]. Furthermore, the hardware components in our hardware trace compressor are modularized and parameterized, allowing the designers to trade off between the achievable compression ratio and the hardware cost in order to satisfy different design objectives.…”

Section: Introductionmentioning

confidence: 99%

A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors

Kao

Huang²,

Huang³

2007

IEEE Trans. Circuits Syst. I

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Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real-time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: 1) branch/ target filtering; 2) branch/target address encoding; 3) Lempel-Ziv (LZ)-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real-time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1 to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1).

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Emerging on-ship debugging techniques for real-time embedded systems

Cited by 39 publications

References 0 publications

Real-time fault injection using enhanced on-chip debug infrastructures

Real-time fault injection using enhanced on-chip debug infrastructures

Low Cost Debug Architecture using Lossy Compression for Silicon Debug

A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors

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