Emerald: A Bus Style Designer

Tseng, Chia-Jeng; Siewiorek, D.P.

doi:10.1109/dac.1984.1585813

Cited by 3 publications

(1 citation statement)

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“…This work solves the clique partitioning problem by grouping nodes with the maximum number of common neighbours to find the minimum number of cliques in a graph. Tseng and Siewiorek continue their work in [19], as they develop a design generator called 'Emerald' that produces functional level structures from a behavioral description. The designs generated from this approach for a mainframe computer, the IBM System/370 was restricted to the ISPS description, and showed great similarities to designs created by human experts.…”

Section: Global Algorithmic Approachesmentioning

confidence: 99%

A Graph Heuristic Approach for the Data Path Allocation Problem. (c2022)

Makhoul¹

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The current escalation in usage and complexity of modern digital systems, and the emergence of Very-Large Scale Integration (VLSI) has led to a huge design productivity gap in the chip design industry. It is well established that the annual growth of the number of transistors on a chip surpasses that of transistors handled by a fi xed-sized design team. This gap, represented by \Moore's law of engineers", raises the necessity for more efficient approaches to automatically design these advanced frameworks. This paper aims to reduce the design productivity gap by presenting a new algorithm to optimize chip design automation in terms of runtime and solution quality. More speci cally, this automation process known as high-level synthesis (HLS), targets the datapath allocation problem in VLSI design. In this context, datapath allocation represents one of the major steps in HLS along with scheduling and partitioning. To optimize this allocation problem, a variation of the Fiduccia-Mattheyses (FM) algorithm is presented. The algorithm starts with a schedule as input and partitions it into available hardware resources using a modifi ed version of the Fiduccia-Mattheyses algorithm to t the datapath allocation problem. The algorithm is tested on various benchmarks and favorable results are reported. The results show that the algorithm performs well while generating sub-optimal solutions.

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Section: Global Algorithmic Approachesmentioning

confidence: 99%

A Graph Heuristic Approach for the Data Path Allocation Problem. (c2022)

Makhoul¹

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Algorithms for hardware allocation in data path synthesis

Devadas

Newton

1989

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

204

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Abstract-The most creative step in synthesizing data paths executing software descriptions is the hardware allocation process. New algorithms for the simultaneous costlresource constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a twodimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. We present simulated-annealingbased algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit and interconnect allocation, while effectively exploring the existing tradeoffs in the design space.

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Automated Synthesis of Digital systems

Parker

1984

IEEE Des. Test. Comput.

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Emerald: A Bus Style Designer

Cited by 3 publications

References 1 publication

A Graph Heuristic Approach for the Data Path Allocation Problem. (c2022)

A Graph Heuristic Approach for the Data Path Allocation Problem. (c2022)

Algorithms for hardware allocation in data path synthesis

Automated Synthesis of Digital systems

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