Embedded software in real-time signal processing systems: application and architecture trends

Paulin, Pierre; Liem, Clifford; Cornero, Marco; Nacabal, F.; Goossens, Gert

doi:10.1109/5.558716

Cited by 54 publications

(33 citation statements)

References 17 publications

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“…Comprehensive survey of the works on computer-aided design of application-specific programmable processors have been conducted by Goosens [18], Paulin [19], and Marwedel [20]. In particular, a great deal of effort has been made in combining retargetable compilation technologies and design of instruction sets [22]- [26].…”

Section: Related Work and Our Contributionsmentioning

confidence: 99%

Exploring the diversity of multimedia systems

Kin¹,

Lee

Mangione-Smith

et al. 2001

IEEE Trans. VLSI Syst.

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Abstract-We evaluate the validity of the fundamental assumption behind application-specific programmable processors: that applications differ from each other in key parameters which are exploitable, such as the available instruction-level parallelism (ILP), demand on various hardware resources, and the desired mix of function units. Following the tradition of the CAD community, we develop an accurate chip area estimate and a set of aggressive hardware optimization algorithms. We follow the tradition of the architecture community by using comprehensive real-life benchmarks and production quality tools. This combination enables us to build a unique framework for system-level synthesis and to gain valuable insights about design and use of application-specific programmable processors for modern applications. We explore the application-specific programmable processor (ASSP) design space to understand the relationship between performance and area. The architecture model we used is the Hewlett Packard PA-RISC [1] with single level caches. The system, including all memory and bus latencies, is simulated and no other specialized ALU or memory structures are being used. The experimental results reveal a number of important characteristics of the ASSP design space. For example, we found that in most cases a single programmable architecture performs similarly to a set of architectures that are tuned to individual application. A notable exception is highly cost sensitive designs, which we observe need a small number of specialized architectures that require smaller areas. Also, it is clear that there is enough parallelism in the typical media and communication applications to justify use of high number of function units. We found that the framework introduced in this paper can be very valuable in making early design decisions such as area and architectural configuration tradeoff, cache and issue width tradeoff under area constraint, and the number of branch units and issue width.Index Terms-Application-specific programmable processor, instruction level parallelism, mediabench, mediaprocessor, system-level synthesis.

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Section: Related Work and Our Contributionsmentioning

confidence: 99%

Exploring the diversity of multimedia systems

Kin¹,

Lee

Mangione-Smith

et al. 2001

IEEE Trans. VLSI Syst.

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“…Compilers today, while better than before, still suffer from a large performance penalty compared to programs directly written in assembly language [Bhattacharyya et al 2000;Paulin et al 1997]. This forces many performance-critical kernels to be written directly in assembly.…”

Section: Introductionmentioning

confidence: 99%

“…This forces many performance-critical kernels to be written directly in assembly. Assembly programming has well-known disadvantages: more tedious, expensive, and error-prone code development, difficulty in porting between different platforms, and a longer time-to-market between successive implementations [Bhattacharyya et al 2000;Paulin et al 1997]. Further, optimizations that benefit from whole-program analysis, such as memory allocation, cannot be captured by rewriting certain kernels.…”

Section: Introductionmentioning

confidence: 99%

An optimal memory allocation scheme for scratch-pad-based embedded systems

Avissar

Barua

Stewart

2002

ACM Trans. Embed. Comput. Syst.

259

233

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This article presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in microcontrollers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM, and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead, the memory units are mapped to different portions of the address space. Caches are avoided due to their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software.Current practice typically leaves it to the programmer to partition the data among different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal, relative to the profile run, among all static partitions for global and stack data. For the first time, our allocation scheme for stacks distributes the stack among multiple memory units. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Results from our benchmarks show a 44.2% reduction in runtime from using our distributed stack strategy vs. using a unified stack, and a further 11.8% reduction in runtime from using a linear optimization strategy for allocation vs. a simpler greedy strategy; both in the case of the SRAM size being 20% of the total data size. For some programs, less than 5% of data in SRAM achieves a similar speedup.

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“…However, validating requirements via an inspection checklist can be problematic when trying to validate all the possible functional interactions by inspecting one requirement at a time. This problem is even more pronounced in embedded software systems, where the correct interaction of certain functionalities represent characteristics unique to embedded systems, must be addressed during validation [20,21]. The key characteristics of embedded systems [9] are:…”

Section: Introductionmentioning

confidence: 99%

Interactive requirements validation for reactive systems through virtual requirements prototype

Aceituna

Lee

2011

2011 Model-Driven Requirements Engineering Workshop

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-Adequate requirements validation can prevent errors from propagating into later development phases, and eventually improve the quality of software systems. However, validating natural language requirements is often difficult and error-prone. An effective means of requirements validation for embedded software systems has been to build a working model of the requirements in the form of a physical prototype that stakeholders can interact with. However, physical prototyping can be costly, and time consuming, extending the time it takes to obtain and implement stakeholder feedback. We have developed a requirements validation technique, called Virtual Requirements Prototype (VRP), that reduces cost and stakeholder feedback time by allowing stakeholders to validate embedded software requirements through the interaction with a virtual prototype.I.

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Embedded software in real-time signal processing systems: application and architecture trends

Cited by 54 publications

References 17 publications

Exploring the diversity of multimedia systems

Exploring the diversity of multimedia systems

An optimal memory allocation scheme for scratch-pad-based embedded systems

Interactive requirements validation for reactive systems through virtual requirements prototype

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