Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS

Chou, Mao-Hsuan; Chang, Ya-Tin; Tsai, Tsung-Hsien; Lu, Tsung-Che; Liao, Chien Chang; Kuo, H.H.; Sheen, Ruey-Bin; Chang, Chih-Hsien; Hsieh, Kenny; Loke, Alvin L. S.; Chen, Mark

doi:10.1109/vlsicircuits18222.2020.9162789

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Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS

Cited by 6 publications

References 3 publications

Exploring A Comprehensive Review of Non-linear and Composite Phase Frequency Detectors within PLL Frameworks

Exploring A Comprehensive Review of Non-linear and Composite Phase Frequency Detectors within PLL Frameworks

A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor

A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration

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