Embedded boundary scan

Treuren, B.G. Van; Miranda, J.M.

doi:10.1109/mdt.2003.1188258

Cited by 10 publications

(3 citation statements)

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“…Inadequate validation of the software system may lead to higher fixing cost. The condition can be worse if the defect is found in the field and requires recalling product from customers [16]- [18]. A successful and effective testing process reduces a defect lifecycle as short as possible; thus, most testing processes are involved in the early stage of development process.…”

Section: Limited Resources (Memory Usage)mentioning

confidence: 99%

Automated Compilation Test System for Embedded System

Ishak

Hwan

Teh

et al. 2019

MST

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Embedded system testing involves testing an integration of software and hardware. It is increasingly difficult to evaluate the functionality of each module within a short time because of the increasing number of tests required. In this paper, a novel stepwise methodology involving the use of an automated compilation test system (ACTS) is proposed, to improve the quality of testing and optimize the testing time using automation. Using the proposed method, the testing coverage can be maximized, while minimizing the manual work and testing time required. This ACTS was used to automate the test code compilation and execution for different hardware modules. The proposed method significantly saved the testing time by approximately 56.42%, compared to the existing method, while ensuring quality testing performance. AbstrakSistem Uji Kompilasi Otomatis untuk Sistem Sisipan. Pengujian sistem sisipan melibatkan menguji suatu penyatuan perangkat lunak dan perangkat keras. Menjadi bertambah sulit untuk mengevaluasi fungsionalitas masing-masing modul dalam waktu singkat karena peningkatan jumlah pengujian yang diperlukan. Di dalam karya tulis ini, diusulkan suatu metodologi bertahap baru penggunaan suatu sistem uji kompilasi otomatis (ACTS), untuk meningkatkan kualitas pengujian dan mengoptimalkan waktu pengujian dengan menggunakan otomatisasi. Dengan menggunakan metode yang diusulkan, jangkauan pengujian dapat dimaksimalkan, sekaligus meminimalkan waktu manual dan waktu pengujian yang diperlukan. ACTS ini digunakan untuk mengotomatisasi kompilasi kode uji dan eksekusi untuk modul-modul perangkat keras yang berbeda. Metode yang diusulkan mengamankan waktu pengujian secara signifikan mendekati 56,42%, dibandingkan dengan metode yang ada, sekaligus memastikan kinerja pengujian kualitas.

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Section: Limited Resources (Memory Usage)mentioning

confidence: 99%

Automated Compilation Test System for Embedded System

Ishak

Hwan

Teh

et al. 2019

MST

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“…There are many more constraints that must be applied to a circuit to prevent the test from affecting the operation of a system (e.g., active backplane signals). These issues have been covered in great detail by [1], [2], [3], [4], [5] and [6].…”

Section: Board-centric Testing Vs Multidrop Testingmentioning

confidence: 99%

“…The software used to read the data is an additional TestStep [4] feature to the Lucent Test Flow Control Language™ (TFCL™). TFCL was invented to provide a flexible language for embedded testing applications.…”

Section: International Test Conferencementioning

confidence: 99%

JTAG-based vector and chain management for system test

Treuren

Peterson

Miranda

IEEE International Conference on Test, 2005.

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We present an embedded boundary-scan test vector management solution that ensures the correct version of test vectors is applied to the Unit Under Test (UUT). This new vector management approach leverages the system-level boundary-scan multi-drop architecture employed in some high availability electronic systems. Compared to previous methods that do not use system-level boundary-scan resources for vector management, this new approach ensures that the correct boundary-scan vectors are retrieved from the UUT without affecting its operation and requires minimal UUT functionality to execute. The performance and effectiveness of this technique is shown using an actual design example that has been realized in a new product.

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Design for Testability — Structured Test Approaches

Integrated Circuit Test Engineering

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Embedded boundary scan

Cited by 10 publications

References 0 publications

Automated Compilation Test System for Embedded System

Automated Compilation Test System for Embedded System

JTAG-based vector and chain management for system test

Design for Testability — Structured Test Approaches

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