Electrostatic discharge protection in silicon-on-insulator technology

Voldman, Steven H.; Hui, David; Warriner, L.; Young, D.; Williams, R.; Howard, J. K.; Gross, V.; Rausch, W.; Leobangdung, E.; Sherony, M.; Rohrer, Norman J.; Akrout, C.; Assaderaghi, F.; Shahidi, G.

doi:10.1109/soi.1999.819858

Cited by 25 publications

(29 citation statements)

References 6 publications

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“…In addition to the above-mentioned challenges in ESD protection for all advanced CMOS technologies, silicon-on-insulator (SOI) technology [7,8] presents distinctive challenges due to the buried oxide (BOX) layer underneath the active silicon film. While reducing parasitic capacitance [9,10], the BOX also makes vertical and deep body ESD structures no longer feasible.…”

Section: Technology Trendsmentioning

confidence: 99%

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Cao

Chun

Salman

et al. 2011

Microelectronics Reliability

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Section: Technology Trendsmentioning

confidence: 99%

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Cao

Chun

Salman

et al. 2011

Microelectronics Reliability

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“…SOI lateral diodes for ESD protection can be constructed using a hybrid device that utilizes both the p-channel MOSFET and n-channel MOSFET without the use of body contact structure [10,11,[13][14][15][16]. Using the p-and n-channel source/drain implants, a mask can be placed on the MOSFET gate structure where the p-channel MOSFET source/drain implant forms the anode, and the n-channel MOSFET source/drain forms the cathode.…”

Section: Soi Esd Design: Soi Lateral Diode Structurementioning

confidence: 99%

“…The mask to define the p þ and n þ implants must be placed over the polysilicon-gate structure. In this fashion, the polysilicon-bound diode structure has a polysilicon film with two different dopant types and work functions along the device channel length [13][14][15][16]. With the placement of this structure on a BOX, the trench isolation abuts the BOX film, isolating the polysilicon-bound diode structure from adjacent structures.…”

Section: Soi Esd Design: Soi Lateral Diode Structurementioning

confidence: 99%

“…Since the design is an enclosed gate structure, it is necessary to provide an electrical contact to the lateral SOI gate structure. The electrical contact to the gate must be made over the isolation structure [13][14][15][16]. Figure 5.7 shows the ESD robustness of a polysilicon-bound gated diode structure as a function of polysilicon perimeter.…”

Section: Soi Esd Design: Soi Lateral Diode Structurementioning

confidence: 99%

“…Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling [5-9], experimental work and design integration [11][12][13][14][15][16][17][23][24]27], and SOI patents [10,18,19,21,22,25,[26][27][28][29][30][31][32][33][34][35][36][37][38][39][40].Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.…”

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Silicon on Insulator (SOI) ESD Design

2005

Esd

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SOI ESD design is distinct from bulk CMOS ESD design as a result of the buried oxide (BOX) film and the MOSFET floating body region [1,[2][3][4]. The BOX decouples the SOI n-and p-channel MOSFET body region from the silicon substrate [2][3][4]. The BOX region also separates and isolates the p-and n-channel SOI MOSFET. Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling [5-9], experimental work and design integration [11][12][13][14][15][16][17][23][24]27], and SOI patents [10,18,19,21,22,25,[26][27][28][29][30][31][32][33][34][35][36][37][38][39][40].Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.Some of the fundamental distinctions are as follows:No vertical parasitic devices exist.No lateral device exists without formation of a MOSFET gate structure; hence, SOI MOSFETs, diodes, and resistors utilize gate structures.Vertical shallow trench isolation (STI)-bound p þ anode/n-well cathode diode structure does not exist in SOI technology.n-well-to-substrate ESD diode elements do not exist in SOI technology.Parasitic CMOS-based pnpn structures do not exist in SOI technology.There are no vertical diode elements, hence no advantage to the area dependency in the design of structures. ESD: Circuits and Devices Steven H. VoldmanThere are no guard ring structures needed in SOI technology.There are no local substrate contact guard rings for SOI devices.n-and p-well regions do not exist.Bulk ''floating gate tie-downs'' and well tie-downs do not exist.Unique electrical connections need to be established with the substrate region in SOI technology.As a result of the above issues, although the basic concepts in SOI ESD design are the same, there are significant differences in the physical layout and device choices [1]. Additionally, even with the direct mapping of circuits, the ESD response circuit can be significantly different, leading to new ESD issues and failure mechanisms.Where at first glance, the presence of the BOX appears to be a serious decrement to SOI ESD design [2-5], the issues above can lead to significant advantages over bulk CMOS silicon ESD design [1].The lack of vertical parasitic devices leads to a reduction of the complexity of device-todevice interactions. In bulk CMOS, a significant number of ESD failures and concerns are unanticipated interactions between adjacent elements and adjacent circuits; in SOI, this is not true. In bulk CMOS ESD design, the interaction between adjacent elements and circuits leads to complex ESD design rules and logical-to-physical checking computer-aided design (CAD) tools. In SOI, ESD design is significantly simplified because of the elimination of these unexpected interactions and cu...

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Electrostatic Discharge (ESD) Design: Diode Design

Voldman

2005

Esd

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Diodes are the basic building blocks of ESD design. Diodes are used for ESD input node devices [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15], mixed-voltage interface input environments [16][17][18][19][20][21][22], ESD rail-to-rail devices [23,24], and ESD power clamps [25][26][27][28]. Diodes and gated-diodes serve as good ESD protection elements in many technologies: CMOS , radio frequency (RF) CMOS [12,13,15], BiCMOS silicon germanium [29][30][31][32], and silicon-on-insulator (SOI) [33][34][35][36][37][38].The key to good ESD design of diode structures is establishment of good current uniformity, establish internal ballasting, and avoidance of defect mechanisms that reduce the ESD effectiveness. Quantification of these design aspects can be achieved experimentally by the ESD results, simulation, or failure analysis. In this chapter, we will discuss the design features of ESD diode structures for ESD networks.Provide a solution that establishes a low-voltage trigger element, which can discharge a high current.Provide spatially uniform current density within the diode structure.Avoid localized Joule heating.Avoid electrical connections that exceed the breakdown voltage of the dielectric films.Operate the device under the diode breakdown voltage.Improve thermal stability of the diode structure. ESD: Circuits and Devices Steven H. VoldmanThe ability to provide a low-voltage trigger element can be achieved by the following means:Use diode elements in the forward bias mode of operation to achieve low turn-on voltage.Minimize the diode series resistance.Minimize the number of diode elements in series.Maximize the number of parallel diode elements.High current can be achieved in diode ESD structures by the following means:Low-resistance interconnects, via and contact structure and design.Minimize the space between the anode and cathode regions.Minimize the spacing between anode and cathode physical contacts.Maximize the number of anode and cathode contacts that exist at minimum spacing.Maximize the anode perimeter-to-area ratio.Low-resistance salicide films on anode and cathode.Heavily doped anode and cathode regions.Spatial uniformity is achieved in the diode ESD structure by the following means:Provide design spatial and electrical symmetry in the metal and contact design.Ballasting perpendicular to the direction of the diode current flow.Avoidance of localized heating in the diode structure can be achieved by the following means:Provide design symmetry in the metal and contact design.Introduce ballasting perpendicular to the diode current flow. (e.g., lateral ballasting) via design or semiconductor process.Utilize vertical structures to avoid localized heating near the isolation surface.Increase doping concentrations to increase the intrinsic temperature (T i ) and reduce the Joule heating of the diode regions.Avoidance of failure of the diode structure in gated-diode structures due to dielectric breakdown can be achieved by the following means:Avoid diode gate-to-power rail direct connections.Avoid diode ga...

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Electrostatic discharge protection in silicon-on-insulator technology

Cited by 25 publications

References 6 publications

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Silicon on Insulator (SOI) ESD Design

Electrostatic Discharge (ESD) Design: Diode Design

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