Electronic properties of low-temperature InP

Deep centers in undoped semi-insulating InP

“…First, T b , peaked at 170K, is largely reduced by Fe-doping (see Fig. 16 It has been shown that a deep donor, which is due to the single ionized donor transition P In 0/+ , is resonant with the conduction band (located at E C + 0 12 eV), making LT-InP highly conductive. Although T b has been reported in Fe-doped SI InP by many authors, 7,9,15 it has never appeared as a prominent trap.…”

“…3). 16,17 The activation energies of 0.33 eV (T d ) and 0.44 eV (T b ) found in this study and in a similar study (using DLTS and TSC measurements on annealed undoped n-InP and SI InP, respectively 15 ), are very close to those for P In +/++ found in LT-InP. Secondly, T d , peaked at 130K, also becomes a prominent trap only in undoped or lightly Fe-doped InP.…”

He-plasma assisted epitaxy for highly resistive, optically fast InP-based materials

“…In the case of GaAs, the intrinsic defect EL2 is used in the production of semi-insulating substrates, while highly resistive epitaxial GaAs can be produced by the introduction of nonradiative defects associated with excess As in a procedure involving low-temperature growth and postgrowth annealing. 1,2 Low growth temperature methods have also been applied to InP, [2][3][4][5][6] and recently a combination of low growth temperature and Be doping has resulted in ultrafast photoresponse at 1.55 m wavelength in multiquantum well structures on InP. 7 In this letter, a plasma assisted epitaxial technique is presented and used to produce both high resistivity InP and optically fast, 1.55 m wavelength, InGaAsP quaternary lattice matched to InP.…”

SEE analysis of digital InP-based HBT circuits at gigahertz frequencies

“…To implement an InP buffer in the substrate, a high-resistivity material must be used to prevent leakage between devices and the buffer must be lattice matched to the InP substrate. Presently, low-temperature grown InP has shown low resisitivities [16] insufficient to use in a VLSI fabrication process where device isolation is required.…”