Electron Tunneling Enhancement in MoS₂/Hexagonal Boron Nitride/Multilayer Graphene Heterostructures by Bubble Formation

Abstract

Unintentional bubbles are formed when manufacturing devices using two-dimensional materials. Usually, these bubbles affect device performance degradation, but in the case of memory devices, an additional charge trap can be expected. We investigate the direct surface potential of bubbles formed in a hexagonal boron nitride (hBN)/multilayer graphene (MLG) heterostructure. Specifically, we study the electron transfer improvement by increasing the memory window of a MoS 2 /hBN/MLG heterostructure in floating gate memory owing to bubbles formed at the hBN/MLG heterointerface. This characterization of bubbles containing molecules such as water or hydrocarbon in two-dimensional material heterointerfaces can promote the understanding of charge carrier tunneling in two-dimensional material heterostructures.

Demonstration of Nonvolatile Storage and Synaptic Functions in All-Two-Dimensional Floating-Gate Transistors Based on MoS2 Channels

“…The difference between positive V t and negative V t is regarded as the memory window. When the scan voltage range is ±60 V, the memory window reaches 107.8 V; specifically, the memory window ratio is up to 89.8%, which is much larger than the reported values. − From the blue curve, the memory window also linearly increases with the sweeping range of V bg so that the storage performance of the device is enhanced, which is consistent with the progressive charge trapping process. The stored charge density ( n ) in the graphene floating-gate is also estimated from the expression n = (Δ V t × C FB )/ q , where q is the electron charge (1.6 × 10 –19 C), Δ V t is the shift of V t , C FB is the capacitance between the back gate and floating-gate, modeled as C FB = ε 0 ε r / t ox , with ε 0 being the vacuum permittivity, ε r being the relative permittivity of SiO 2 , and t ox being the thickness of SiO 2 (285 nm).…”

Negative Differential Interlayer Resistance in WSe2 Multilayers via Conducting Channel Migration with Vertical Double-Side Contacts

“…This triggers a spatial redistribution of charge carriers along the thickness. − Additionally, a vertical double-sided contact configuration has recently been demonstrated to be a preferable platform for evaluating the spatial modification and separation of the conducting channel within 2D vdW multilayers by comparing the obtained drain current with respect to bottom contact and top contact, respectively . Nevertheless, this distinct transport feature would be masked substantially by undesired chemical residues, surface adsorbates such as oxygen and water molecules, and contact resistance. − This would obstruct the attainment of clear insight into the carrier transport behavior of 2D vdW multilayers, particularly for the variation of the channel vertical position under electrostatic drain and gate bias conditions. This, in turn, would hinder the achievement of optimal device performance using 2D multilayers.…”