Electron-beam mask writer EBM-6000 for 45 nm HP node

Yashima, J.; Ohtoshi, Kenji; Nakayamada, Noriaki; Anze, Hirohito; Katsumata, Takehiko; Iijima, Takafumi; Nishimura, Rieko; Fukutome, Syuuichiro; Miyamoto, Nobuo; Wake, Seiji; Sakai, Yusuke; Sakamoto, Shinji; Hara, Shigehiro; Higurashi, Hitoshi; Hattori, Kiyoshi; Saitô, Kenichi; Kendall, Rodney; Tamamushi, Shuichi

doi:10.1117/12.728917

Cited by 5 publications

(2 citation statements)

References 4 publications

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“…EBM-7000 inherits basic architecture for its system from previous tool, EBM-6000 (7) , i.e. 50kV acceleration voltage, variable shaped beam (VSB), vector scan and continuous motion stage with variable stage speed (8) .…”

Section: System Configurationmentioning

confidence: 99%

Electron beam mask writer EBM-7000 for hp 32nm generation

Kamikubo¹,

Ohtoshi²,

Nakayamada³

et al. 2009

SPIE Proceedings

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Optical lithography is facing resolution limit. To overcome this issue, highly complicated patterns with high data volume are being adopted for optical mask fabrications. With this background, new electron beam mask writing system, EBM-7000 is developed to satisfy requirements of hp 32nm generation. Electron optical system with low aberrations is developed to resolve finer patterns like 30nm L/S. In addition, high current density of 200 A/cm 2 is realized to avoid writing time increase. In data path, distributed processing system is newly built to handle large amounts of data efficiently. The data processing speed of 500MB/s, fast enough to process all the necessary data within exposure time in parallel for hp32nm generation, is achieved. And this also makes it possible to handle such large volume dense data as 2G shots/mm 2 local pattern density.In this paper, system configuration of EBM-7000 with accuracy data obtained are presented.

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Section: System Configurationmentioning

confidence: 99%

Electron beam mask writer EBM-7000 for hp 32nm generation

Kamikubo¹,

Ohtoshi²,

Nakayamada³

et al. 2009

SPIE Proceedings

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“…The simulation results agreed with the measurement results to a high accuracy of ±2 nm. The corrected data was used for exposure by an electron beam (EBM-6000) 15 ; PAL-009 16 resist was used on the mask to obtain a high CD accuracy. The mask consisted of a 51-nm-thick LR-TaBN absorber on a Cr buffer layer on the Si cap layer of a Mo/Si multilayer.…”

Section: Conditionsmentioning

confidence: 99%

Process liability evaluation for EUVL

Aoyama¹,

Tawarayama²,

Tanaka³

et al. 2009

Alternative Lithographic Technologies

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This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

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