Electron barrier height change and its influence on EEPROM cells

Sethi, Riti; Kim, U.S.; Johnson, I.; Cacharelis, P.; Manley, M.

doi:10.1109/55.145041

Cited by 11 publications

(3 citation statements)

References 3 publications

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“…In modern microelectronics the transport of electrons and holes across ultra-thin dielectric barriers is of considerable interest. Well-known examples are the injection of carriers into gate oxides of metal-oxide-semiconductor-fieldeffect-transistors ͑MOSFETs͒ 1,2 leading to a long-term shift of their threshold voltage ͑so-called degradation͒, the strong tunnel currents during the erase mode of electrically erasable programmable read only memories ͑EPROMs͒, 3 the currentvoltage characteristics of metal-insulator-semiconductor ͑MIS͒ solar cells, [4][5][6][7] or the tunneling leakage occurring in memory cells. 8,9 Modeling and numerical simulation of these currents rely not only on realistic distribution functions for the charge carriers, but also on a good knowledge of the quantum-mechanical transmission probability for ultra-thin barriers.…”

Section: Introductionmentioning

confidence: 99%

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Schenk¹,

Heiser

1997

Journal of Applied Physics

210

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Direct and Fowler-Nordheim tunneling through ultra-thin gate dielectrics is modeled based on an approach for the transmission coefficient ͑TC͒ of a potential barrier that is modified by the image force. Under the constraint of equal actions the true barrier is mapped to a trapezoidal pseudobarrier resulting in a TC very close to the numerical solution of the Schrödinger equation for all insulator thicknesses and for all energies of the tunneling electron. The barrier height of the pseudopotential is used as a free parameter and becomes a function of energy in balancing the actions. This function can be approximated by a parabolic relation which makes the TC of arbitrary barriers fully analytical with little loss of accuracy. The model was implemented into a multidimensional device simulator and applied to the self-consistent simulation of gate currents in metal-oxide-semiconductor ͑MOS͒ capacitors with gate oxides in the thickness range 15 Å-42 Å. Excellent agreement with experimental data was obtained using a thickness-independent tunnel mass m ox ϭ0.42 m 0. Thanks to the CPU-time efficiency of the method the simulation of a complete MOS-field-effect-transistor with dominating gate current becomes possible and shows the potential for further applications.

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Section: Introductionmentioning

confidence: 99%

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Schenk¹,

Heiser

1997

Journal of Applied Physics

210

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“…[1] This new process could at the same time change many aspects of the MOS device, such as device reliability properties, etc., besides enhancing the carrier mobility. [2][3][4][5][6] It has been reported that the strained-Si/Si 1−x Ge x /Si substrate might have a thinner gate oxide than the unstrained one. [7][8][9][10] However, there is no detailed information given in their reports.…”

Section: Introductionmentioning

confidence: 99%

Retarded thermal oxidation of strained Si substrate

et al. 2014

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Strained Si is recognized as a necessary technology booster for modern integrated circuit technology. However, the thermal oxidation behaviors of strained Si substrates are not well understood yet despite their importance. In this study, we for the first time experimentally find that all types of strained Si substrates (uniaxial tensile, uniaxial compressive, biaxial tensile, and biaxial compressive) show smaller thermal oxidation rates than an unstrained Si substrate. The possible mechanisms for these retarded thermal oxidation rates in strained Si substrates are also discussed.

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“…1,2 Reducing the barrier height of silicon dioxide is another approach to lowering the operating voltage. The operating voltage can be done by increasing the silicon surface roughness, 3 changing the doping concentration of polysilicon gates, 4,5 implanting fluorine into silicon before gate oxidation, and gate oxidation in NO or similar gases. 6 Thin fluorinated oxides have been investigated and found to have lower barrier height than silicon dioxide.…”

mentioning

confidence: 99%

Growing High-Performance Tunneling Oxide by CF[sub 4] Plasma Pretreatment

Chang

Lee

Lei

et al. 2003

J. Electrochem. Soc.

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Thin tunneling oxides grown on a CF 4 pretreated silicon substrate were prepared and investigated for the first time. The tunneling current of the CF 4 -treated oxide is about three orders of magnitude higher than that of thermal oxide; furthermore, the stressinduced anomalous current and low electric field leakage current were greatly suppressed. The improvement was attributed to the incorporation of fluorine in the oxide region. Both control and CF 4 -treated devices exhibited comparable channel mobility. However, pretreatment with CF 4 markedly improved the reliability of the insulator. This oxide is highly promising for fabricating low-voltage electrically erasable and programmable read-only memories ͑EEPROMs͒ without increasing the complexity of the process.

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Electron barrier height change and its influence on EEPROM cells

Cited by 11 publications

References 3 publications

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Retarded thermal oxidation of strained Si substrate

Growing High-Performance Tunneling Oxide by CF[sub 4] Plasma Pretreatment

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