Electromigration for advanced Cu interconnect and the challenges with reduced pitch bumps

Islam, Nokibul; Kim, Gwang; Kim, KyungOe

doi:10.1109/ectc.2014.6897266

Cited by 16 publications

(7 citation statements)

References 9 publications

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“…This increase of the local current density is known as the current crowding. The current crowding effect leads to a local temperature rise around the void due to joule heating [16] that further accelerates the void growth and the whole process continues till the void is large enough to break the line and the process is shown in Figure 5.…”

Section: Em Failure Mechanismsmentioning

confidence: 99%

“…As a result voids will be formed on some parts of the interconnection [14] and hillock due to the accumulation of the metal atoms will be formed on different parts of the interconnection [5]. The presence of voids will increase the resistance [15] [16] of the interconnection or even open, while increased mechanical stress may result in dielectric fractures and leakage between adjacent interconnects in Figure 3 and Figure 4. On the other hand, the presence of hillock will cause short circuit between the adjacent interconnections if the hillock is developed side-way, and short circuit between the different levels of interconnections if it is developed vertically and punch through the inter-metal dielectric.…”

Section: Introductionmentioning

confidence: 99%

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A Review of the Study on the Electromigration and Power Electronics

Rahman¹,

Musa²,

Neher³

et al. 2016

JECTC

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Electromigration is a main challenge in the pursuit of power electronics, because physical limit to increase current density in power electronics is electromigration (EM), whereas much higher electrical current and voltage are required for power electronics packaging. So the effect of EM is an important issue in applications where high current densities are used, such as in microelectronics and related structures (e.g., Power ICs). Since the structure size of integrated circuits (ICs) decreases and the practical significance of this effect increases, the result is EM failure. On the other hand, in the next generation power electronics technology electrical current density is expected to exceed 10 7 A/cm 2 which is another challenge. This review work has been carried out to identify the mechanism of EM damage in power electronics (e.g., pure metallization and solder joints) and also how to control this kind of damage.

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Section: Em Failure Mechanismsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Review of the Study on the Electromigration and Power Electronics

Rahman¹,

Musa²,

Neher³

et al. 2016

JECTC

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“…In recent years, thermal compression bonding has been preferred for pitch below 40 µm since reflow and placement accuracy are deemed inadequate for such fine pitch [7][8]. In this study, we focused on thermal compression bonding (TCB) to address technology requirements for the current and future processors and logic devices.…”

Section: Introductionmentioning

confidence: 99%

“…Lower current density also helps improve electro-migration at the solder interface. Further implementation of bump-on-trace (BOT) or bump-on-lead (BOL) or bump-on-package (BOP) as referred in the literature [6][7][8] is expected to significantly increase the interconnect density on the substrate leading to lower number of substrate layers, therefore reduce the package thickness and fabrication cost while simultaneously achieve the smallest form factors in all three dimensions.…”

Section: Introductionmentioning

confidence: 99%

Reliability assessment of thermally compression bonded copper pillar on organic and ceramic substrates

Bhattacharya¹,

Lewis²,

Wu³

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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The ultimate goal of this study is to address and overcome the critical barriers for implementing a low cost high yield manufacturing process using thermal compression bonding of copper pillars to a high density organic substrate with the aid of a nonconductive paste. First, a conventional reflow bonding of the copper pillars to the organic and ceramic substrate was conducted and reliability after air-to-air thermal cycling was compared for baseline evaluation. The selected test vehicle for this step was a pressure sensor module where ASIC and MEMS chips were mounted on both sides of a 6-layer organic and a 6-layer ceramic substrate using a solder paste and an underfill material. Thermal cycling of the constructed functional module showed superior reliability for the ceramic substrate compared to the organic. In the second step, a design of experiments was conducted to optimize process conditions for thermal compression bonding of the copper pillars in ASIC chips to both ceramic and organic substrates using a nonconductive paste in lieu of an underfill. The assembled substrates were thermally cycled under similar conditions to evaluate thermal reliability performance and mechanical integrity of the bonding. Results show better performance for the ceramic substrate compared to the organic. The conditions for dispensing a nonconductive paste and thermal compression bonding using an automated machine have been optimized for further evaluation and scaling up to manufacturing where dispensing of the nonconductive paste, placement of chips, and thermal compression bonding can be achieved in-situ with a single assembly tool with reduced cycle time. The substrate for high throughput manufacturing is a 3-layer (dielectric) high density organic allowing direct landing of fine pitch copper pillar to the conductor traces without any landing pads.

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“…Although various criterions may lead to wide variation in results, packaging reliability tests with different criterions were found from the literatures and the industrial standards. For example, the failure criterions for direct current electrical reliability measurement used in a single conference included relative resistance change at 5% [1], 10% [2][3][4][5][6], 15% [7,8], 20% [3,[9][10][11], or a resistance threshold [12]. After reviewing typical TSV reliability paper, it was interesting to note that a large variety of criterions were used in the literatures [13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

A Study on Electrical Reliability Criterion on Through Silicon Via Packaging

Lwo

Tseng

Tseng³

2016

Journal of Electronic Packaging

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Three-dimensional (3D) structure with through silicon via (TSV) technology is emerging as a key issue in microelectronic packaging industry, and electrical reliability has become one of the main technical subjects for the TSV designs. However, criteria used for TSV reliability tests have not been consistent in the literature, so that the criterion itself becomes a technical argument. To this end, this paper first performed several different reliability tests on the testing packaging with TSV chains, then statistically analyzed the experimental data with different failure criteria on resistance increasing, and finally constructed the Weibull failure curves with parameter extractions. After comparing the results, it is suggested that using different criteria may lead to the same failure mode on Weibull analyses, and 65% of failed devices are recommended as a suitable termination for reliability tests.

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Electromigration for advanced Cu interconnect and the challenges with reduced pitch bumps

Cited by 16 publications

References 9 publications

A Review of the Study on the Electromigration and Power Electronics

A Review of the Study on the Electromigration and Power Electronics

Reliability assessment of thermally compression bonded copper pillar on organic and ceramic substrates

A Study on Electrical Reliability Criterion on Through Silicon Via Packaging

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