Electroless Gold Plating on III–V Compound Crystals

D'Asaro, L.A.; Nakahara, S.; Okinaka, Y.

doi:10.1149/1.2130040

Cited by 42 publications

(37 citation statements)

References 7 publications

(21 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Metal contacts to these materials are important for applications such as next‐generation computing platforms, optoelectronics, and LEDs, among others 5. While only a smattering of papers have examined galvanic displacement of noble metals (Au and Pd) on InP and GaAs, alloying or intermetallic formation between the noble metals and these compound semiconductors has been reported 6. Galvanic displacement on III–V semiconductors may therefore form the basis for development of a mechanically strong, direct electronic contact between the metal nanoparticle–semiconductor interfaces, important for novel nanoscale metallic interconnects and direct semiconductor–nanoparticle wiring.…”

Section: Methodsmentioning

confidence: 99%

Synthesis and Patterning of Gold Nanostructures on InP and GaAs via Galvanic Displacement

Nezhad

Aizawa

Porter

et al. 2005

Small

View full text Add to dashboard Cite

Plugging into III–Vs: Crystalline, sub‐100 nm gold nanoparticles are formed via simple galvanic displacement reactions on InP and GaAs surfaces (see images). The reactions require only four ingredients (gold salt, semiconductor, water, and dilute acid) and result in firmly bound gold nanoparticle arrays on the surface. The chemistry can be patterned via AFM‐tip‐mediated scribing of the sub‐5‐nm‐thick surface oxide to reveal the underlying semiconductor, leading to galvanic displacement only in the exposed areas.

show abstract

Section: Methodsmentioning

confidence: 99%

Synthesis and Patterning of Gold Nanostructures on InP and GaAs via Galvanic Displacement

Nezhad

Aizawa

Porter

et al. 2005

Small

View full text Add to dashboard Cite

show abstract

“…These hybrid nanostructures exhibit enhanced efficiency in photo‐induced charge separation and photocatalysis 54, 55. In addition to semiconductor nanostructures, metallization of large‐area semiconductor wafers with uniform metal films has been studied in the past several decades for creating ideal contacts (e.g., Schottky and Ohmic contacts) in electronics,56–61 but direct growth of metal nanoparticles with well‐controlled anisotropic morphologies on semiconductor wafers is still challenging and few successes have been achieved 62…”

Section: Introductionmentioning

confidence: 99%

Metal Nanoplates on Semiconductor Substrates

Sun

2010

Adv Funct Materials

View full text Add to dashboard Cite

Growth of anisotropic metal nanostructures with well‐defined shapes on large‐area semiconductor substrates represents a challenge to synthesize hybrid materials with complex functionalities. This Feature Article highlights the approach recently developed in our group for growing nanoplates made of noble metals (e.g., Ag, Pd, Au/Ag alloy) on semiconductor wafers (e.g., GaAs and Si), which are widely used in the semiconductor industry. In the typical syntheses, only the semiconductor wafers and pure aqueous solutions of metal precursors are involved in the reaction. The absence of surfactant molecules, organic solvents, catalysts, etc. in the syntheses makes this strategy suitable for the formation of metal/semiconductor hybrid materials with clean metal/semiconductor interfaces. The mechanism for the selective growth of metal nanoplates on semiconductor substrates is extensively discussed. The as‐grown metal nanoplates protrude out of the substrates to expose most of their surface areas to the surrounding environment, leading to be favorable for some applications, such as catalysis and surface‐enhanced Raman scattering.

show abstract

“…ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.192.114 19. Downloaded on 2015-06-08 to IP…”

mentioning

confidence: 99%

Electrochemical Deposition of Nanoscaled Palladium Catalysts for 65 nm Copper Metallization

Chang

Hsu

Fang

et al. 2003

J. Electrochem. Soc.

View full text Add to dashboard Cite

The preparation of nanoscaled palladium ͑Pd͒ particles for catalyzation of electroless copper ͑Cu͒ plating has been investigated in this research. Nanosized Pd catalysts were electrochemically deposited on Si/SiO 2 /Ta x N substrates using displacement activation and sensitization activation, and their formation and microstructures were characterized. By displacement activation, large Pd particles with nonuniform size distribution from 20 to 200 nm are observed, resulting in subsequent rough and discontinuous Cu films electrolessly deposited on these Pd catalysts. In comparison, tremendous, small, and uniform Pd nanoparticles of about 10 nm are obtained by sensitization activation as fine nucleation sites for following electroless deposition of smooth and conformal Cu films. Nucleation, growth, coalescence, and then connection and film growth steps are observed in the formation process of Cu films. No preferred orientation of both electrolessly deposited Cu films is found. Well-controlled, electrochemically deposited nanoscaled Pd catalysts and uniform Cu films can be used as 65 nm Cu interconnect metallization.When the sizes of material structures are scaled down to nanometers, surfaces will occupy tremendous portions of whole materials and play very important roles. Surface effect, small-size effect, and even quantum effects are thus caused and severely affect the physical and chemical properties of these nanosized materials. Especially the insufficient coordination sites and high surface energy resulting in the high activity of these large amounts of surface atoms renders the application of nanosized materials to catalysts very possible. 1 For example, nickel, iron, and cobalt ferromagnetic nanoparticles have attracted a lot of interest as catalysts for the preparation of carbon nanotubes. 1 Copper with low electrical resistivity, good mechanical properties, and high electromigration resistance is used for interconnect metallization in dual-damascene structures of ultralarge-scale integrated ͑ULSI͒ circuits. 2-4 Electrochemical Cu plating, one of the Cu deposition techniques, becomes much attractive in semiconductor manufacturing industry because of its low processing temperature, high step coverage, high selectivity, and low cost. 4-7 However, sputtered Cu seed layers are still necessary for Cu electroplating, while their deposition technique is not adequate due to the insufficient gap-filling capability when the linewidths of integrated circuits ͑ICs͒ for next generation decrease to 65 nm. 8 Since that, the growth of Cu films with high selectivity and good step coverage by electroless deposition has been intensively studied. [9][10][11][12][13][14][15] One of the most important factors to influence the quality and morphologies of the electrolessly deposited Cu films is the activation step to seed the inert substrates prior to the nucleation and growth of Cu films. A large amount of uniformly distributed, nanoscaled catalysts dominates the success of activation process and subsequent electroless plating. Two ...

show abstract

Electroless Gold Plating on III–V Compound Crystals

Cited by 42 publications

References 7 publications

Synthesis and Patterning of Gold Nanostructures on InP and GaAs via Galvanic Displacement

Synthesis and Patterning of Gold Nanostructures on InP and GaAs via Galvanic Displacement

Metal Nanoplates on Semiconductor Substrates

Electrochemical Deposition of Nanoscaled Palladium Catalysts for 65 nm Copper Metallization

Contact Info

Product

Resources

About