Electrodeposition of photoresist: optimization of deposition conditions, investigation of lithographic processes and chemical resistance

Schnupp, R; Baumgartner, Ramona; Kühnhold, R; Ryssel, H.

doi:10.1016/s0924-4247(00)00344-7

Cited by 14 publications

(7 citation statements)

References 3 publications

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“…A disadvantage of using an elevated bath temperature is the faster degradation of the photoresist due to loss of volatile components [13]. In order to achieve thinner coatings without using elevated bath temperatures it is possible to add InterVia 3D-N TC thickness controller to the 3D-N. A similar study has been done previously with InterVia 3D-P [14].…”

Section: Edpr Thickness Optimizationmentioning

confidence: 98%

Controlled-width track in through silicon via using 3D holographic photolithography with modified electrodepositable photoresist

Toriz-Garcia¹,

Williams²,

McWilliam³

et al. 2009

J. Micromech. Microeng.

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We present a novel lithographic process for patterning controlled-width tracks onto anisotropically micromachined silicon. The technique is based on the use of computer-generated holographic masks with a custom alignment and exposure tool. Experimental and simulation results are presented. 3D holographic photolithography significantly reduces the problem normally present with photolithography on non-planar surfaces-namely diffractive line broadening. A negative-acting electrodepositable photoresist (InterVia 3D-N) is used in the study. Its deposition onto the 3D substrate is optimized by modification of coating temperature and thickness and of pre-exposure bake conditions. We show the successful patterning of a constant-width 8 μm line down the sloping sidewall of a 500 μm thick silicon wafer. This is beyond the conventional resolution limit and indicates the potential of the technique for realizing high-density vertical routing in electronic packages and MEMS.

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Section: Edpr Thickness Optimizationmentioning

confidence: 98%

Controlled-width track in through silicon via using 3D holographic photolithography with modified electrodepositable photoresist

Toriz-Garcia¹,

Williams²,

McWilliam³

et al. 2009

J. Micromech. Microeng.

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“…Contrary to what one might expect, the thickness of electrodeposited photoresist is not practically controllable with voltage because the process is current terminated once a conformal and defect-free coating is achieved. As shown in figure 6(c), the thickness can be substantially controlled by varying the emulsion temperature or the concentration of 2octanone in photoresist emulsion [23]. At higher temperature, the micelles more readily flow and form a complete insulating coating, thus terminating the coating process at a thickness as small as ∼5 μm.…”

Section: Optimization Of Electrodeposited Photoresist Coatingmentioning

confidence: 99%

“…The sample was then placed in a beaker of commercially available Intervia 3DP developer, which is mainly tetramethylammonium hydroxide. An alternate developer is a 5% sodium carbonate solution [23]. Both of these developer solutions etch Al, providing another reason why Cu is preferred over Al electrodes.…”

Section: 24mentioning

confidence: 99%

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A full description of a scalable microfabrication process for arrayed electrowetting microprisms

Hou¹,

Zhang

Smith³

et al. 2009

J. Micromech. Microeng.

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Most electrowetting and liquid crystal optical devices are created by standard planar microfabrication. Arrayed electrowetting microprisms are a newer approach that offers unique performance, but which requires a challenging non-planar microfabrication process. This paper reviews a full description of a scalable fabrication process for an ∼1500 element array of ∼150 μm size electrowetting microprisms. The description includes creation of high aspect-ratio sidewalls, using a conventional i-line mask aligner to vertically pattern electrodes, conformal hydrophobic dielectric deposition, self-assembled and volume-controlled liquid dosing and module sealing. Also presented is a theoretical model which explores the resolution limits for vertically patterned electrodes. In addition to creating a first-generation fabrication process for arrayed electrowetting microprisms, this work may be further useful to investigators seeking methods of forming 3D arrayed electro-optic, electro-chemical or electro-mechanical devices.

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“…To handle this problem much effort was spent in developing of an electro deposited photo resist process. The resist chosen 6 was originally intended to be used for printed circuit board lithography, but it has also been used for three-dimensional pattering of anistropically etched silicon structures [13], [14]. Exposure of the resist was done with a mask aligner 7 equipped with special optics which enables high resolution (depth of focus) over large topographies.…”

Section: ) Patterningmentioning

confidence: 99%

Elastomer chip sockets for reduced thermal mismatch problems and effortless chip replacement, preliminary investigations

Norberg¹,

Dejanovic²,

Hesselbom

2003

IEEE Trans. Adv. Packag.

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To avoid the problem with thermo-mechanical stress induced fatigue using conventional flip-chip mounting of bare chips, an elastic chip socket has been developed.The socket is made by casting silicone elastomer into micro structured silicon molds to form micro bump arrays. After the elastomer is cured and released from the mold, a metal layer is deposited and patterned.A chip is placed in the socket utilizing guiding structures for chip self alignment. The chip is then held in place by a spring loaded back-plate which can also serve as a heat sink for highly effective chip cooling. Since no adhesives, underfills or solders are used, the rework process becomes very simple and it can also be repeated many times for the same socket. Initial contact resistance and thermo-mechanical robustness measurements indicates that this type of sockets could work as a superior replacement for conventional flip-chip technologies in many applications. The particular design of the contact bumps results in metal structures that resemble (although up side down) and are scalable as those in the Chip-First technology.Preliminary thermal shock experiments from room temperature to liquid nitrogen and back show good survival. Thus, this new chip interconnect method indicates the possibility of getting the advantages of the Chip-First technology while eliminating the demand of placing the chip first. The concept will work for chips with rim positioned pads as well as for high density area arrays.

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Electrodeposition of photoresist: optimization of deposition conditions, investigation of lithographic processes and chemical resistance

Cited by 14 publications

References 3 publications

Controlled-width track in through silicon via using 3D holographic photolithography with modified electrodepositable photoresist

Controlled-width track in through silicon via using 3D holographic photolithography with modified electrodepositable photoresist

A full description of a scalable microfabrication process for arrayed electrowetting microprisms

Elastomer chip sockets for reduced thermal mismatch problems and effortless chip replacement, preliminary investigations

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