Electrically driven optical proximity correction

Abstract

Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance.Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

Role of Design in Multiple Patterning: Technology Development, Design Enablement and Process Control

“…As a result, design-aware electrical setting of process control requirements is important [8]. Design-aware optical proximity correction [9,10] and mask inspection [11] have already been shown to have significant advantages.…”

Review of computational lithography modeling: focusing on extending optical lithography and design-technology co-optimization

“…A parameter such as the maximum effective sample size [20] . Figure 6 Illustration of case that minimizing EPE error might not correspond to minimize device saturation current error and vice versa [26] .…”

On comparing conventional and electrically driven OPC techniques

“…It has been suggested that this change in the target of OPC produces an increase in electrical accuracy, a decrease in the fragmentation size, and a faster algorithm runtime. [1][2][3][4][5][6]8 In a typical edge-based SDOPC flow, a mask is generated and the simulated contour is examined and compared to the design layout. All edges are examined to see if they are within a tolerable distance from the intended position.…”

“…In EDOPC, correction is repeated until the electrical properties meet electrical requirements. [1][2][3][4][5][6] Using electrical objectives results in a smaller fragmentation requirement for an equivalent current accuracy as SDOPC. Number of candidate OPC solutions accepted by EDOPC is orders of magnitude higher than SDOPC leading to potentially much faster convergence.…”