Electrical Test Method for Interconnect Open Defects in 3D ICs

Abstract

In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

A testable design for electrical interconnect tests of 3D ICs

“…The test methods proposed in [14] and [15] request us that ESD input protection circuits inside each of the dies are designed so as for supply current to flow in our tests. A testable designed protection circuit proposed in [14] is shown in Fig.2(b).…”

“…It requests us to design ESD input protection circuits inside a die so as to be tested by the test method. Thus, we had proposed two kinds of DFT methods for ET-Scan tests [14,15]. We prototyped an IC embedding the ESD input protection circuits and showed feasibility of the test with the prototyping IC by some experiments [14,15].…”