Electrical performance of vertical natural capacitor for RF system-on-chip in 32-nm technology

Liu, En‐Xiao; Li, Er‐Ping

doi:10.1109/epeps.2011.6100179

Cited by 4 publications

(3 citation statements)

References 7 publications

(8 reference statements)

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“…5, a uniform power grid on through-silicon interposer just beneath the chip with a metal layer distribution of w = 10 m, t = 2 m and a pitch of 20 m is presented to demonstrate the accuracy if the proposed modelling method. One voltage source connected at (6,6) and three current loads connected at (4,6), (6,2) and (8,4) are applied to the power grid. The wire resistance between two adjacent nodes in the power grid is computed as 17.2 m from wire geometry.…”

Section: Numerical Examplesmentioning

confidence: 99%

“…The resistance between two adjacent nodes is computed as 17.2 m . One voltage source connected at (6,6) and three current loads connected at (4,6), (6,2) and (8,4) are applied to the power grid. The voltage source is set to 1 V and each dc current load sinks at 100 mA.…”

Section: Numerical Examplesmentioning

confidence: 99%

“…The efficient modeling and analysis for voltage drops in the power grids of through-silicon interposer (TSI) is deployed with an equivalent circuit model of the VNCAPs [7,8]. Numerical results of the systematic modeling approach are presented with conclusions.…”

Section: Introductionmentioning

confidence: 99%

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Systematic modeling of on-chip power grids with decaps in TSV-based 3D chip integration

2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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Efficient modeling of power supply noises is crucial for a robust power supply design, especially with increase in the size of on-chip power grids due to emerging 3D chip integration technology. As the power grid is interconnected vertically by through-silicon vias (TSVs), operational currents required by each functional device in integrated circuits (ICs) are supplied through vertical power and ground TSVs, and horizontal power grids. Fast switching speed of the devices become complicated the accurate analysis of the worst case power supply noises. In this paper, a systematic modeling of on-chip power grids with decoupling capacitors -VNCAPsused in TSV-based chip integration technology is presented using novel equivalent decap circuit model. The equivalent circuit model will be numerically validated and integrated into an efficient modeling for impedance profile of on-chip power grids and analysis of power supply noises in TSV-based 3D chip integration technology. IntroductionWith emerging 3D chip integration technology for integrated circuits (ICs) and systems into small form factor, lower power consumption and high band-width, and rising the functional density and lowering the noise margins, power integrity becomes a limiting factor for the performance of the devices [1]. Reduced supply voltages and increased current demands have resulted in stringent constraints on a robust power supply design for the 3D ICs [2]. The power supply voltage should be reliable distributed in order for the devices to function properly. Operation voltage V dd for the device is decreasing with new emerging technology node, while the required current is increasing with the increase in integration functional density [3]. The overall supply voltage across the load fluctuates because of the voltage drops resulted from the resistive and inductive nature of the power grid in the 3D ICs and the current demand of the local load devices. Estimating and analyzing these voltage drops, which plays a crucial role in the design and test of integrated circuits, is challenging because of increased complexity of on-chip interconnects.Power and ground distribution networks for 3-D integrated circuits contain millions of interconnects or nodes. Since the power and ground networks are considered as linear network, the formulation of the analysis modeling should be straight forward. However, solving the linear system of the network is computationally intensive due to the large grid size. Suppose the power distribution network has N rows and N columns in grid, the resulting resistance matrix to solve the linear system of the network is N 2 x N 2 . The size of the resistance matrix will increase in quadratic when increasing the power grid size. Conventional linear solvers are computationally inefficient to solve the system due to the large size of the power distribution network.

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