Electrical Overstress Failure Analysis in Microcircuits

Smith, Jack S.

doi:10.1109/irps.1978.362816

Cited by 25 publications

(7 citation statements)

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“…c, --K 2 = dt dx P Equation [2] and its equivalent forms is the General EOS/ESD equation. It describes the failure process for any material whether a conductor, semiconductor or insulator.…”

Section: The Heat Equationmentioning

confidence: 99%

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General EOS/ESD Equation

Smith

1997

Proceedings Electrical Overstress/Electrostatic Discharge Symposium

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It is proposed the general EOS/ESD equation is nothing more than the heat equation driven by electrical power. Further that virtually all EOS/ESD failures are rooted in the thermal process. Support is given for the three materials; metals, semiconductors and particularly insulators. We compare the failure of an earthen dam to that of dielectric breakdown and show the remarkable similarity in behavior. A consequence of the General equation is that latency is not a legitimate consideration.

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Section: The Heat Equationmentioning

confidence: 99%

“…We will begin with metals, move on to the semiconductor and finish off with insulators. You will see the same equation or one of its identical forms [2] really applies to all three kinds of materials.…”

Section: General Equation Supportmentioning

confidence: 99%

General EOS/ESD Equation

Smith

1997

Proceedings Electrical Overstress/Electrostatic Discharge Symposium

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“…Electrical overstress occurs when a higher-than-rated voltage or current induces a hot-spot temperature beyond specifications for short periods of time [Alexander 1978, Canali 1981, Smith 1978. Hot-spot development typically occurs at a semiconductor junction as the current flow increases to accommodate the additional stress in the device.…”

Section: Electrical Overstressmentioning

confidence: 99%

The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Pecht¹

1993

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“…[9] Eq. 2 shows that the failure current is proportional to the cross-sectional area of the sensor (hd).…”

Section: A Energy Failure Mechanismmentioning

confidence: 99%

Field-induced charged device model testing of magnetoresistive recording heads

Wallash

Proceedings Electrical Overstress/Electrostatic Discharge Symposium

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This paper reports on the behavior of a magnetoresistive (MR) recording head in external electric fields for the first time. Both energy and voltage failure thresholds during field-induced charged device model (CDM) testing are measured. An equivalent circuit model for the MR 0ead is constructed and used in PSPICE circuit simulations. The first atomic force microscope (AFM) data and SEM micrographs of CDM damaged MR heads are also presented and analyzed.

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Electrical Overstress Failure Analysis in Microcircuits

Cited by 25 publications

References 0 publications

General EOS/ESD Equation

General EOS/ESD Equation

The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Field-induced charged device model testing of magnetoresistive recording heads

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