Electrical modeling of Through Silicon and Package Vias

Bandyopadhyay, Tapobrata; Chatterjee, Ritwik; Chung, Duke Whan; Swaminathan, Madhavan; Tummala, Rao

doi:10.1109/3dic.2009.5306542

Cited by 112 publications

(59 citation statements)

References 9 publications

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“…Based on [4,5] and (6), the effects of both applied voltage and operating temperature on the depletion radius r On the other hand, we would like to point out that in the fabrication of a copper TSV, a very thin barrier layer, such as Ta, TaN or TiN, must be introduced between copper and SiO 2 , and its work function (Ta/TaN ∼ 4.25 eV) is different from that of copper (∼ 4.7 eV), which is taken into account in our calculation. With respect to Fig.…”

Section: Electrothermal Properties Of Tsv Pairsmentioning

confidence: 99%

“…For example, lumped-element circuit models of singlelayer TSVs are derived in [2,4] and [5], respectively, and some closedform equations are given to determine their parasitic parameters and time delay of the transmitted signal. Slow-wave characteristics of a pair of TSVs used for power delivery in 3-D chip package are examined in [6], electromagnetic modeling of TSV interconnections using cylindrical modal basis functions is performed in [7], reduction technique of TSV capacitance is proposed in [8], with temperature dependent electrical characteristics of TSV interconnects studied in [9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Electrothermal Effects in High Density Through Silicon via (Tsv) Arrays

Zhao¹,

Wang²,

Yin

2011

PIER

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Abstract-Electrothermal effects in various through silicon via (TSV) arrays are investigated in this paper. An equivalent lumped-element circuit model of a TSV pair is derived. The temperature-dependent TSV capacitance, silicon substrate capacitance and conductance are examined for low-, medium-, and high-resistivity silicon substrates, respectively. The partial-element equivalent-circuit (PEEC) method is employed for calculating per-unit-length (p.u.l.) resistance, inductance, insertion loss and characteristic impedances of copper and polycrystalline silicon (poly-Si) TSV arrays, and their frequencyand temperature-dependent characteristics are treated rigorously. The modified time-domain finite-element method (TD-FEM), in the presence of a set of periodic differential-mode voltage pulses, is also employed for studying transient electrothermal responses of 4-and 5-TSV arrays made of different materials, with their maximum temperatures and thermal crosstalk characterized thoroughly.

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Section: Electrothermal Properties Of Tsv Pairsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Electrothermal Effects in High Density Through Silicon via (Tsv) Arrays

Zhao¹,

Wang²,

Yin

2011

PIER

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“…8. The dimensions of the pad hosting the 40 TSV are , in order to avoid alignment problems. The transceiver includes individual ESD protection, a buffer for signal integrity and a weak pull down for each TSV.…”

Section: A Tsv Redundancy Policy and Circuit Collecting Yieldmentioning

confidence: 99%

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Beanato

Giovannini

Cevrero

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…The RLC modeling as a function of the physical parameters of a TSV has been presented in [10]. An electrical TSV model is proposed and compared by 3D EM solver considering the semiconductor effects in [11]. Models for the coupling noise of TSV are proposed in [12].…”

Section: Introductionmentioning

confidence: 99%

“…Many studies have been conducted to model and analyze TSVs by constructing equivalent circuit models [4][5][6][7][8][9][10][11][12][13]. In [4,5], an efficient modeling method for a TSV based on cylindrical modal basis functions has been studied and has demonstrated high accuracy, close to that of full-wave simulations.…”

Section: Introductionmentioning

confidence: 99%