Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an SRAM cell

Abstract

International audienceThis abstract presents an electrical model of an SRAM cell exposed to a pulsed Photoelectrical Laser Stimulation (PLS), based on our past model of MOS transistor under laser illumination. The validity of our model is assessed by the very good correlation obtained between measurements and electrical simulation. These simulations are capable to explain some specific points. For example, in theory, a SRAM cell under PLS have four sensitive areas. But in measurements only three areas were revealed. A hypothesis was presented in this paper and confirm by electrical simulation. The specific topology of the cell masks one sensitive area. Therefore the electrical model could be used as a tool of characterization of a CMOS circuits under PLS

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

“…They also came to the conclusion that the bit-set/bit-reset fault model is the relevant one as they did not obtain any bit-flip type fault. They also validated their results through simulation using the electrical model of transistors exposed to laser stimulation described in [9], [11], [12]. Finally, they obtained further validation of their results by performing fault injection experiments on the RAM memory of a microcontroller.…”

“…The drain of MP2 did not react as expected: the sensitive area was masked. In [9] Sarafianos et al made the hypothesis that this phenomenon was due to the comparatively small surface of the drain of MP2 compared to a counter-balancing effect of the photocurrent induced in the shared drain of transistors MN2 and MN3, MN3 is the access transistor of the SRAM (see figure 5a). Note that MP2's drain has a drain surface smaller than that of MN2/MN3 which makes this phenomenon happen (the photocurrent magnitude is proportional to the drain surface).…”

“…In previous works, Sarafianos et al [9] and Roscian et al [10] both studied the fault models that apply to SRAM cells for laser-induced faults. They drew maps of the lasersensitive areas of a 5 transistors SRAM cell using a 50 ns laser pulse duration.…”

Laser-Induced Fault Effects in Security-Dedicated Circuits

“…The ratio of the P+/N-and N+/P-junction areas in this new cell is now 48:5 instead of 8:5 as in the original standard inverter INV2 of the target library. As detailed in [27] for logic gates, and in [7] for SRAM cells, the photocurrents Iph_dp and Iph_dn being proportional to the area of the junctions, this new area ratio between the inverter's PMOS and NMOS transistors allows us to increase Iph_dp compared to Iph_dn and thus to increase Iph_out. The proposed invertor-based sensor is thus more sensible than the original cells (see Fig.…”

“…Previous related work was done in order to derive models of laser shots on CMOS Bulk ICs, especially on SRAM cells [7]. The model validity was assessed by a very good correlation with an experimental laser sensitivity map.…”