2022
DOI: 10.3390/mi13111829
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Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors

Abstract: This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more e… Show more

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Cited by 3 publications
(2 citation statements)
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“…The authors in [19] presented an analysis and optimization tool for spiral planar inductors operated at high frequency, with the capability of determining the inductance and electrical parameters for different planar inductor geometries (e.g., octagonal and hexagonal). An electrical circuit model for a graphene-based on-chip power inductor was introduced in [20]. In relation to fabrication, a planar inductor with NiZn ferrite layers was fabricated using a screen printing method in [21], while, in [22], a planar inductor with a MnZn ferrite layer was presented.…”
Section: Introductionmentioning
confidence: 99%
“…The authors in [19] presented an analysis and optimization tool for spiral planar inductors operated at high frequency, with the capability of determining the inductance and electrical parameters for different planar inductor geometries (e.g., octagonal and hexagonal). An electrical circuit model for a graphene-based on-chip power inductor was introduced in [20]. In relation to fabrication, a planar inductor with NiZn ferrite layers was fabricated using a screen printing method in [21], while, in [22], a planar inductor with a MnZn ferrite layer was presented.…”
Section: Introductionmentioning
confidence: 99%
“…Wang et al study the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model [ 6 ]. Kim et al propose a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling in high-bandwidth memory and demonstrate that the proposed channel structure could reduce dynamic power consumption [ 7 ].…”
mentioning
confidence: 99%