Electrical Interconnection and Bonding by Nano-Locking

Abstract

The growing demand for increased chip performance and stable reliability calls for the development of novel off-chip interconnection and bonding methods that can process good electrical, thermal, and mechanical performance simultaneously as well as superior reliability. A chip bonding method with the concept of “nano-locking” (NL) is proposed: the two surfaces are locked together for electrical interconnection, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. The general applicability of this new method was investigated by applying the method to the die-substrate bonding of two different packages from two different manufacturers. Electrical, optical, and thermal performances as well as reliability tests were carried out. The surface morphology of the bonding package substrates plays an important role in determining the contact resistance at the bonding interfaces. It was shown that samples with different roughness height distribution on the metallic surfaces formed a different total number of contacts and the contact area between the two bonding surfaces under the same bond-line thickness (BLT): a larger number of contact area resulted in a reduced electrical resistance, and thus an improved overall device performance and reliability.