Electrical Enhancement and Higher-K Engineering in Ultra-Thin Atomic Layer Deposited Hf_1-xAl_xO_yFilms

Abstract

We have successfully deposited Hf 1-x Al x O y with Al/(Al+Hf)% ranging from 0 to 25% using an atomic layer deposition (ALD) process which incorporates a sequential metal precursor pulse method. The dielectric crystal phase was confirmed to be a mixed phase of tetragonal and monoclinic using a combination of synchrotron measurement techniques consisting of grazing incidence X-ray diffraction, and grazing incidence extended X-ray absorption fine structure. The crystallization temperature as a function of Al incorporation was assessed by synchrotron X-ray diffraction with in-situ ramp annealing. In metal-oxide-semiconductor (MOS) capacitors we observed an equivalent oxide thickness (EOT) reduction of ∼2 Å compared to HfO 2 for Hf 1-x Al x O y with Al/(Al+Hf)% ≤ 6% annealed near the crystallization temperature of the Hf 1-x Al x O y films. In addition, the leakage current was also reduced by a factor of 10 while maintaining a flatband voltage that is comparable to post deposition annealed (PDA) HfO 2 films processed under identical conditions. This study highlights the importance of understanding the crystallization temperature and its relationship to electrical performance for higher-k phase stabilized Hf 1-x Al x O y films.

Reliability of HfAlO<inf>x</inf> in multi layered gate stack

“…Comparison of dielectrics (A 2 ) annealed at 680 0 C, 700 0 C, and 800 0 C showed that with increase in annealing temperature, Al concentration slightly reduced which could be due to outdiffusion of Al at high temperature [14]. It was found that dielectrics with ~7% Al/(Al+Hf) starts to crystallize at 800 0 C annealing temperature while crystallization temperature decreases for dielectrics with lower Al percentage [22]. Therefore, A 3 with 30 cy HfAlO x showed ~2Å higher film thickness because of a mixed structure of amorphous and crystalline phase formation as compared to other dielectrics (a) Table I).…”

“…Therefore, A 3 with 30 cy HfAlO x showed ~2Å higher film thickness because of a mixed structure of amorphous and crystalline phase formation as compared to other dielectrics (a) Table I). When dielectrics have 4-5% Al, they remain amorphous even after annealing at 700 0 C [22]. As a result, A 2 with 20 Cy HfAlO x annealed at 680 0 C, and 700 0 C showed ~3Å higher thickness as compared to the dielectric annealed at 800 0 C (Table I).…”

“…The native oxide on the 300mm wafers was removed using a TEL Certas TM chemical oxide removal (COR) process [22]. A thin SiO 2 interface layer (IL) was then formed using vapor ozone.…”

“…It was found that after 800 0 C annealing, dielectrics with <2% Al/(Al+Hf) has higher crystallization with a mixed structure of monoclinic and tetragonal phase formation, while increased Al incorporation inhibits the crystallization process [22]. On the other hand, the control device C, with HfO 2 crystallizes into monoclinic phase which is thermodynamically stable phase for HfO 2 [22]. It is known that tetragonal stabilization of HfO 2 results in a higher dielectric constant [6,22].…”

“…Aluminum concentration variation near the high-κ/metal gate interface and near the Si/SiO 2 interface was modulated by varying the thickness and location of the HfAlO x layer in a multi-layered gate stack. While all the dielectrics structures used in this work were subjected to a PDA at 800 0 C, one set of the multi-layered stacks was also annealed at 680 0 C and 700 0 C. We have chosen these three annealing temperatures, because samples having Al/(Al+Hf)% in the range: 0 to 7% have crystallization temperature in the range: 680 0 C to 800 0 C [22]. The reliability characteristic of these dielectric films was investigated by subjecting them to a constant voltage stress.…”