Electrical Design of a High Speed Computer Packaging System

Davidson, E.

doi:10.1109/tchmt.1983.1136188

Cited by 27 publications

(8 citation statements)

References 7 publications

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“…Similar expressions have been developed previously and used to derive wiring rules intended to reduce delay and minimize reflections in package design [4]. We argue in this paper that such "macromodels" can be routinely developed by, and indeed can benefit from, a systematic application of experimental model building procedures in conjunction with dimensional analysis.…”

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confidence: 79%

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Delay macromodels for point-to-point MCM interconnections

Kayssi

Sakallah²

1994

IEEE Trans. Comp., Packag., Manufact. Technol. B

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We develop delay macromodels for lossless as well as lossy point-to-point MCM transmission lines using a systematic model construction procedure that includes dimensional analysis. The result for lossless lines confirms earlier work and extends it to the case of nonlinear drivers and capacitive termination. For lossy lines, we show that dimensional analysis allows us to reduce the complexity of the delay expression without any loss in accuracy. A second-order polynomial fit to a four-argument delay function is shown to yield predictions that are within 5% of detailed circuit simulation at a fraction of the computational cost. We illustrate the applications of these macromodels in studying the effects of packaging technology on signal delay and in sensitivity analysis. Zndex T'ms-Macromodeling, dimensional analysis, multichip module, transmission line, interconnect delay, packaging, sensitivity. I. INTRODUC-ITON N THIS PAPER WE DEVELOP delay expressions for I lossless and lossy point-to-point multichip module (MCM)interconnections and use them to study the effect of technology and circuit parameters on transmission line delay. Similar expressions have been developed previously and used to derive wiring rules intended to reduce delay and minimize reflections in package design [4]. We argue in this paper that such "macromodels" can be routinely developed by, and indeed can benefit from, a systematic application of experimental model building procedures in conjunction with dimensional analysis. For the case of a lossless line driven by a CMOS inverter, we obtain a delay function that is identical in form to what would be derived from a theoretical analysis of an ideal transmission line driven by an ideal voltage source. Significantly, the delay expression was obtained without making any simplifying modezing assumptions. For lossy lines, we show that dimensional analysis allows us to reduce the complexity of the delay expression without any loss in accuracy. A secondorder polynomial fit to a four-argument delay function is shown to yield predictions that are within 5% of detailed circuit simulation at a fraction of the computational cost.After briefly reviewing our macromodeling methodology in Section 11, we describe in Section 111 its application to the development of delay equations for lossless and lossy pointto-point MCM interconnections. Section IV describes how the derived delay equations can be used to study the effect of technology parameters on line delay as well as to obtain the sensitivity of the delay to various parameters. We conclude in Section V by suggesting an extension to handle lines with multiple drops, and by reiterating the benefits of the proposed macromodeling scheme. MACROMODELING METHODOLOGYTypically, the design and optimization of electronic systems requires that we establish the dependence of certain "macroscopic" objectives on a set of relevant designable parameters. For instance, we may be interested in keeping simultaneous switching noise on a printed circuit board below a specified thre...

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confidence: 79%

“…The proposed technique is applicable, however, to other modeling situations. For example, macromodels for estimating reflection, coupling, and simultaneous switching noise can be developed and employed to derive wiring rules similar to those in [4]. Furthermore, delay macromodels for multidrop lines can be easily developed.…”

Section: Extensions and Conclusionmentioning

confidence: 99%

Delay macromodels for point-to-point MCM interconnections

Kayssi

Sakallah²

1994

IEEE Trans. Comp., Packag., Manufact. Technol. B

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“…Irregular or multitap interconnects (buses) increase capacitive loading and signal reflections, limiting the maximum switching speed [18,31,20] and reducing available pin bandwidth. Table I demonstrates the problem of static pin allocation in existing microprocessors.…”

Section: Figmentioning

confidence: 99%

“…They all compromise, yielding mediocre network or memory system performance. The difference signalling rates of buses versus point to point interconnects is well documented and typically a factor of 3 or 4 in clock rate [18,31].…”

Section: Figmentioning

confidence: 99%

“…We further assume that the DI-microprocessor reloads its cache lines from its four nearest neighbors, minimizing the routing delay. The higher network clock rate for the DImicroprocessor memory interface is due to the electrical advantages of point-to-point interconnects over multitap bus lines [31,18]. Router delay is based on a number of published implementation studies [17,32] and our own designs [4,8].…”

Section: Memory Interface Performancementioning

confidence: 99%

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