Electrical characterization of n-type cylindrical gate all around nanowire junctionless transistor with SiO2 and high-k dielectrics

Alias, Nurul Ezaila; Sule, Mohammed Adamu; Tan, Michael Loong Peng; Hamzah, Afiq; Saidu, Kabiru Adamu; Mohammed, Sanusi; Aminu, Tijjani Kuda; Shehu, A I

doi:10.1109/icse49846.2020.9166886

Cited by 7 publications

(4 citation statements)

References 11 publications

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“…When the gate oxide thickness is reduced to 1nm, high leakage current was observed in JLT with SiO2 gate oxide. higher dielectric constant in high-k materials help to reduce the leakage current in the device [8]. Surface contact area between the channel and the oxide layers and the thermal conductivity of the oxide materials are the main factors that define the temperature at the center of the channel.…”

Section: Previous Workmentioning

confidence: 99%

Effects of Scaling of Junctionless Transistor Parameters With Silicon Dioxide (Sio2) and Silicon Nitrate (Si3n4) Gate Oxides on the Electrical Characteristics of the Devices

Sule,

Jonathan D,

Njodi

et al. 2023

ETJ

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This research investigated the effects of scaling of parameters of junctionless transistors (JLT) with SiO2 gate oxide and Si3N4 gate oxide on the electrical characteristics of the two devices. It also compared the electrical performance of the two devices as a way of replacing the conventional SiO2 gate oxide with high-k dielectric such as Si3N4 gate oxide. Different JLT were designed and simulated using a technology computer aided device software, sentaurus and extracted the electrical characteristics such as Threshold voltage, subthreshold slope, drain induced barrier lowering, on-state current etc. It was observed that leakage current, DIBL, SS as well as on-state current were significantly improved using Si3N4 as gate oxide in JLT. As a result, on-state to off-state current ratio was greatly increased, hence the speed of the device. The performance was significantly increased to approximately 109 using Si3N4 material for gate length of 10nm and nanowire diameter of 10nm. All these were achieved because of the high dielectric constant, k of the Si3N4 which is higher than that of SiO2. Similarly, Si3N4 has also has high energy band gap which considerably help in reducing the leakage current and other short channel effects (SCEs).

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Section: Previous Workmentioning

confidence: 99%

Effects of Scaling of Junctionless Transistor Parameters With Silicon Dioxide (Sio2) and Silicon Nitrate (Si3n4) Gate Oxides on the Electrical Characteristics of the Devices

Sule,

Jonathan D,

Njodi

et al. 2023

ETJ

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“…Hence, [2] also proposed to use the same materials in the design and adaptation of cold storage room for the umudike community and environs. Many studies have been conducted on the development of thermal insulation materials from natural fibers such as maize husk, maize cob, groundnut shell, coconut pith and paddy straw [6], cotton seed hulls [7], durian peel and coconut coir [8], Saline Jose tall wheatgrass [9], eggplant stalks [10], tamarind hulls [11] and cotton stalk fibers [12]. [13] stated that thermal insulators are materials that are designed to have high R-value.…”

Section: Research Objectivementioning

confidence: 99%

Development and Characterization ofCamel’s food (Piliostigmathonningii)Insulator for Lagging Application

Lawal,

Gital

2023

IJASRE

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Due to the growing concern for renewable and biodegradable thermal insulation materials motivated by the pending energy crisis, global warming and the environmental impact of the waste product after their useful life, many researchers have worked on the thermal and physical properties of various insulators without giving much consideration to the mechanical properties. Therefore, this paper proposes to investigate the mechanical properties of developed Camel’s food (Piliostigma thonningii) insulator for lagging application. Camel’s foot (Piliostigma thonningii L.) is a leguminous plant found growing abundantly as a wild uncultivated plant resource in many parts of Nigeria. The leaves and the bark fibers of the plant were prepared in form of insulation boardsof thicknesses of 10, 20, 30 40, and 50mm using natural rubber latex as a binder. The ratio of the fiber to the binder in composition was 1:1, 1:2, 1:3 and 1:4.The test results showed that the insulation boards from bark fibers of the plant had good mechanical properties. The properties measured range as follows: ultimate tensile strength (11.66 to 6.96M. Pa); compression strength (0.09 to 0.07 M.Pa), flexural modulus (2545.96 to 2184.07 M.Pa)and flexural strength (53.09 to 29.96 M.Pa). According to the test results, it can be concluded that these insulation boards from the bark fibers of the plant had excellent mechanical properties.

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“…The primary requirement of Junctionless architecture is high uniform doping concentration from source to drain of (10 19 -10 20 cm -3 ) to sustain high current during ON state and total depletion of the channel during OFF state conditions. The concept of high-k spacers has been presented to improve the device's scalability and operation [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Ramakrishnan,

Alias,

Hamzah

et al. 2023

J. Phys.: Conf. Ser.

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Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5μA/μm and Ion/Ioff is 3.2×107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621×105 S/μm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices.

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Electrical characterization of n-type cylindrical gate all around nanowire junctionless transistor with SiO2 and high-k dielectrics

Cited by 7 publications

References 11 publications

Effects of Scaling of Junctionless Transistor Parameters With Silicon Dioxide (Sio2) and Silicon Nitrate (Si3n4) Gate Oxides on the Electrical Characteristics of the Devices

Effects of Scaling of Junctionless Transistor Parameters With Silicon Dioxide (Sio2) and Silicon Nitrate (Si3n4) Gate Oxides on the Electrical Characteristics of the Devices

Development and Characterization ofCamel’s food (Piliostigmathonningii)Insulator for Lagging Application

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

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