Electrical characterization of model-based dummy feature insertion in Cu interconnects

Doong, K.Y.-Y.; Lin, Kemao; Tseng, Tzyy-Jang; Lu, Yi-Chun; Lin, Shio Jean; Hung, L.J.; Ho, Paul S.; Hsieh, Sunnys; Young, K.K.; Liang, Mong–Song

doi:10.1109/icmts.2004.1309307

Cited by 5 publications

(6 citation statements)

References 7 publications

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“…The objective function of the existing optimization approaches [3,4] is to minimize the difference between the highest effective window density H and the lowest effective window density L , i.e. min( H À L ).…”

Section: Existing Minimum-range Approachesmentioning

confidence: 99%

“…Overpolishing the metal can decrease the depth of field of the lithography process, whereas underpolishing can increase the probability of short circuits. Dishing and erosion have been proven to be related to layout pattern density [3], and the most efficient way to reduce them is to add non-functional metal lines, so-called dummy metal features, to increase the layout pattern uniformity. Although dummy metal features may change the capacitance between interconnects and slow down the device, the technique is efficient and popular in the industry.…”

Section: Introductionmentioning

confidence: 99%

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Design for manufacturability: IC layout density optimization by minimum-variance method

Lin

Doong

Chen

2010

Journal of the Chinese Institute of Industrial Engineers

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Design for manufacturing is important in the deep-submicron regime. Increasing integrated circuit (IC) layout uniformity by adding non-functional metal lines in the empty area, so-called dummy feature filling, is an efficient and effective way to reduce pattern-induced topography variation in the chemicalmechanical polishing (CMP) process of IC fabrication. Most existing dummy feature filling methods for IC layout density optimization seek to minimize the effective density range ( H À L ), where H is the highest and L is the lowest effective density calculated by CMP models. This objective function is not suitable for designs with a wide pattern-density range. First, the minimum value of the effective density range ( H À L ) may be fixed because L or H is constrained by chip design and, second, all effective densities will be brought as close as possible to H , making the final effective density distribution inappropriate for process recipe development. Here, we propose a new objective functionminimize the overall effective density variance 2 d . This overcomes the limitations of existing minimumrange approaches. Because linear programming methods for solving minimum-variance problems are time consuming, a mean-based heuristic method is proposed with reduced computational cost. Experiments on two large-sized IC designs showed that the proposed minimum-variance dummy filling method not only achieved the minimum effective density range, but also minimized the effective density variance of the designed layouts.

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Section: Existing Minimum-range Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design for manufacturability: IC layout density optimization by minimum-variance method

Lin

Doong

Chen

2010

Journal of the Chinese Institute of Industrial Engineers

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“…Dummy filling is an efficient and effective DFM-method for increasing layout uniformity by filling non-functional dummy shapes in unoccupied area and thus reducing pattern-induced process variation in IC fabrication processes. It is the most popular way to improve the layout uniformity in industry, which adding non-functional shapes in unoccupied area to improve the uniformity of original layout (Tian et al 2001;Chen et al 2002;Doong et al 2004;Kahng and Samadi 2008). The dummy filling method improves the manufacturability significantly, although the side effect of dummy filling is increasing parasitic capacitance and degrades the circuit speed (Chang et al 2008).…”

Section: Introductionmentioning

confidence: 98%

“…A number of researches were focused on layout density uniformity optimization for CMP process by filling nonfunctional dummy shapes to improve CMP dishing and erosion effects induced by the different CMP removal rate with different layout density (Doong et al 2004), but none is discussed how to optimize the layout design to reduce the thermal effects of FLA process. Figure 2 illustrates the schematic of FLA process (McMahon et al 2007).…”

Section: Introductionmentioning

confidence: 99%

Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing

2010

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In deep sub-micron era, many semiconductor fabrication process variations highly relate to uniformity of IC layout design. Chemical-polishing process and Flash Lamp Anneal (FLA) are two of the crucial processes aiming to increase uniformity of IC. Dummy filling is an efficient and effective Design for Manufacturability method for increasing layout uniformity by filling non-functional dummy shapes onto unoccupied area and thus reducing pattern-induced process variation. However, none are design for the thermal effects of FLA process. FLA process annealed the wafer in high temperature (1250 • C) in a few milliseconds. Wafer surface emissivity determines the amount of heat absorption during FLA process. The temperature variation of FLA process induced by surface emissivity variation of IC layout results in shifts of transistors' electrical parameters. This paper proposed to use genetic algorithm to minimize the emissivity variation of IC layout by filling a series of prescribed dummy patterns with various emissivity. The experimental results from twenty test cases show that 35% emissivity variation reductions can be achieved and moreover the observed temperature deviation during FLA is under 2.8%.

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“…Techniques proposed in references [14], [18] focus on the measurement and analysis of resistance variations, but again, the work is limited to single wire and/or vias. For example, [14] and [15] proposes test structures for characterizing wire resistance mismatch.…”

Section: Introductionmentioning

confidence: 99%

Measuring Power Distribution System Resistance Variations

Helinski

Plusquellic

2008

IEEE Trans. Semicond. Manufact.

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Metal resistance variations in back-end-of-line processes can be significant, particularly during process bring-up. In this paper, we propose a simple method to measure resistance variations in the power distribution system (PDS) eof an IC. Our technique utilizes the PDS because it is an existing distributed resource in all ICs and provides a means of characterizing resistance in the context of the actual circuit design. By applying a set of tests using small on-chip support circuits attached to the PDS, the resistance of components of the PDS can be obtained from the solution to a set of simultaneous equations. The results from hardware experiments involving two sets of test chips fabricated in an IBM 65-nm technology show significant changes in the resistance variation of some components of the PDS as the process evolved.

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Electrical characterization of model-based dummy feature insertion in Cu interconnects

Cited by 5 publications

References 7 publications

Design for manufacturability: IC layout density optimization by minimum-variance method

Design for manufacturability: IC layout density optimization by minimum-variance method

Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing

Measuring Power Distribution System Resistance Variations

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