Elastic DVS Management in Processors With Discrete Voltage/Frequency Modes

Abstract

Abstract-Applying classical dynamic voltage scaling (DVS)techniques to real-time systems running on processors with discrete voltage/frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) versus energy consumption (which is a function of the processor speed).In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions. To make the proposed approach usable in real-world applications, the task model is enhanced to consider some of the real CPU characteristics, such as discrete voltage/frequency levels, switching overhead, task execution times nonlinear with the frequency, and tasks with different power consumption. Implementation issues and experimental results for the proposed algorithm are also discussed.

High performance dynamic voltage/frequency scaling algorithm for real-time dynamic load management

“…The use of elastic scheduling to improve DVS management has been proposed in Marinoni and Buttazzo (2007) and in Zhu et al (2004). Xia et al (2008) proposes energy management based on a feedback control scheduling methodology.…”

“…The maximum operating frequency is a direct consequence of the supply voltage given by f = K((V dd − V th ) )/V dd where K is a constant specific for a given technology, V th is the threshold voltage, and is the velocity saturation index where 1 ≤ ≤ 2 (Saewong and Rajkumar, 2003;Pouwelse et al, 2001). However, the exact form of the power and frequency relation specifically depends on the processor hardware, and can be expressed in terms of CPU speed as a second or third degree polinomial function (Li and Ding, 2001;Aydin et al, 2004;Zhong et al, 2007;Marinoni and Buttazzo, 2007). In this article, the curve of function P (see Fig.…”

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

“…It is that the scalable power supply structure prefers to the constant supply structure in order to high energy efficiency [1]. When the required performance of the target system is lower than the maximum performance, power supply voltage can be dynamically reduced to the lowest possible extent that ensures a proper operation of the system by using the DVS technique [2][3][4][5][6][7][8]. The DVS technique has dynamically varying power supply voltage according to the workload.…”

“…Therefore, the workload prediction and detection are to the essential in DVS technique. Many workload prediction algorithms for the high energy efficiency have been published [4,5]. The reduced power supply V DDL is determined to the workload, process, and delay time.…”

“…But, the reduced power supply V DDL in reported DVS-based processors is commonly 0.5 times of the power supply V DD . And energy efficiency in published DVS-based processors can be improved about 20% to 93% using DC-DC converter and voltage scheduler controlled by the operation system [2][3][4][5][6][7][8]. The power-delay and energy-delay product are the very important factors in DVS technique because the speed penalties due to lowering voltage can be occurred.…”