Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

Arunachalam, V.; Raj, Alex Noel Joseph

doi:10.1049/iet-cds.2013.0457

Cited by 25 publications

(25 citation statements)

References 13 publications

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“…A wide range of literature reports about VLSI FFT/IFFT and Weiner filter design are available, and we discuss a few among them in this section. Arunachalam and Raj [1] concentrated on the trivial multiplications in the input stage of the IFFT unit and replaced them by the proposed "pass-logic". In an orthogonal frequency division multiplexing-based digital transmitter [7], the IFFT processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley-Tukey-based decimation-infrequency (DIF) IFFT architecture.…”

Section: Related Workmentioning

confidence: 99%

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Kumar¹,

Chari²

2019

Journal of Intelligent Systems

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AbstractSpeech signals are usually affected by noises during the communication process. For suppressing the noise signal that is combined with the speech signal, a Wiener filter is adapted in digital hearing aids. Weiner filter plays an important role in noise suppression and enhancement by estimating the relation between the power spectra of the noise-affected speech signal and the noise signal. Power consumption and the hardware requirement are the important problems in adapting Weiner filter for major communication systems. In this work, we implemented an efficient Wiener filter and applied it for noise suppression along with a real-valued fast Fourier transform (FFT)/real-valued inverse FFT processor in digital hearing aids. The pipelined process was adopted for increasing the performance of the system. The proposed Wiener filter was designed to remove the iteration problems in the conventional Wiener filter. The division operation was replaced by an efficient inverse and multiplication operation in the proposed design. A modified architecture for matrix inversion with low computation complexity was implemented. The complete design computation was based on IEEE-754 standard single-precision floating-point numbers. The Wiener filter and the whole system architecture was implemented and designed on a Field Programmable Gate Array platform and simulated to validate the results in Xilinx ISE tools. An efficient reduction in power and area was obtained by adapting the proposed method for speech signal noise degradation. The performance of the proposed design was found to be 50.01% more efficient than that of existing designs.

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Section: Related Workmentioning

confidence: 99%

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Kumar¹,

Chari²

2019

Journal of Intelligent Systems

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“…Here the author has included multipliers and pass logics to enhance the performance improvement parameters but still multipliers are existed in the algorithm needs to eliminated. Nandyala Ramanatha Reddy et.al [12] has introduced a split-radix algorithm for implementation of FFT. With the split-radix algorithm, the number of arithmetic operations were minimized.…”

Section: Literature Surveymentioning

confidence: 99%

A Novel RTL Architecture for FPGA Implementation of 32- Point FFT for High-Speed Application

Mv¹,

Ranjitha²,

Hiremath³

et al. 2017

IOSR JCE

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“…Before going to implement the designer remember to design the pipelined processor with lower memory requirement [6]. The pipelined architecture contains different methods named as single delay path feedback, single delay path commutator, multi path delay feedback, and multipath delay Commutator [7]. Depends on the type, the requirement of the process is also changed.…”

Section: Literature Surveymentioning

confidence: 99%

Efficient Architecture of Combined Radix Dif Algorithm for Mimo-Ofdm Application

Pandiaraj¹

2016

International Journal of Advances in Signal and Image Sciences

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An efficient design of combined radix-2 Single path Delay Feedback (SDF)-Single path Delay Commutator (SDC)-Decimation In Frequency (DIF) algorithm is proposed in this paper which can be used in Orthogonal Frequency Division Multiplexing (OFDM) with Multiple Input Multiple Output (MIMO) applications. The MIMO-OFDM communication system has tremendous and swift growth in various applications used over last decade, especially wireless and digital communication where adaptability, reconfigurability, less chip size, hardware improvements, and lower power consumption are mandatory requirements during communication. The main aim of this structure is to improve the performance of combined Fast Fourier Transform (FFT) for the MIMO-OFDM system and also to reduce the complexity of the hardware.

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Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

Cited by 25 publications

References 13 publications

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

A Novel RTL Architecture for FPGA Implementation of 32- Point FFT for High-Speed Application

Efficient Architecture of Combined Radix Dif Algorithm for Mimo-Ofdm Application

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