Efficient VLSI design of CAVLC decoder of H.264 for HD videos

Mukherjee, Rajarshi; Banerjee, Anupam; Chakrabarti, Indrajit; Dutta, Pranab; Ray, Ajoy Kumar

doi:10.1109/ised.2017.8303918

Cited by 2 publications

(4 citation statements)

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“…For instance, Mukherjee et al [11]. proposed CAVLC decoder using VLSI design with a view for enhancing transmission of HD videos without prejudice to the area, with the possibility of integration with the rest of the H.264 video coder blocks.…”

Section: Related Workmentioning

confidence: 99%

“…In article [17] the authors demonstrate Matlab code that can act as a basis for hardware implementation of (CAVLC) encoder/decoder to process High Definition video sequences. The aforementioned research [11,15] tried working on a reduction of computational complexity, based on Innovative approaches. But they did not mention the depth of PSNR changes and Power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…CONSUMPTION AND FPGA AREA ANALYSIS COMPARISON BETWEEN THE PROPOSED APPROACH , NOVA[22], AND MUKHERJEE ET AL[11] …”

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confidence: 99%

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International Journal of Electronics and Telecommunications

Hamdy¹,

Zekry²,

Mohamed³

2020

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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International Journal of Electronics and Telecommunications

Hamdy¹,

Zekry²,

Mohamed³

2020

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“…The accuracy to decide the search window size in [2] is very high, and, accordingly, the memory access time is less than the case of using the conventional full-search Motion Estimation (FSME) process. Although the previous techniques greatly reduce the memory access time, their very-large-scale integration (VLSI) implementation is not easy [17]. They are not suitable for hardware implementation as they lose the regularity of data flow, but they can greatly reduce the computational complexity.…”

Section: Introductionmentioning

confidence: 99%

High-Efficient Video Transmission for HDTV Broadcasting

Ismail¹

2019

The Future of Television - Convergence of Content and Technology

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Before broadcasting a video signal, redundant data should be removed from the transmitted video signal. This redundancy operation can be performed using many video coding standards such as H.264/Advanced Video Coding (AVC) and H.265/High-Efficient Video Coding (HEVC) standards. Although both standards produce a great video resolution, too much data are considered to be still redundant. The most exhaustive process in video encoding process is the Motion Estimation (ME) process. The more the resolution of the transmitted video signal, the more the video data to be fetched from the main memory. This will increase the required memory access time for performing the Motion Estimation process. In This chapter, a smart ME coprocessor architecture, which greatly reduces the memory access time, is presented. Data reuse algorithm is used to minimize the memory access time. The discussed coprocessor effectively reuses the data of the search area to minimize the overall memory access time (I/O memory bandwidth) while fully using all resources and hardware. This would speed up the video broadcasting process. For a search range of 32 × 32 and block size of 16 × 16, the architecture can perform Motion Estimation for 30 fps of HDTV video and easily outperforms many fast full-search architectures.

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Efficient VLSI design of CAVLC decoder of H.264 for HD videos

Cited by 2 publications

References 5 publications

International Journal of Electronics and Telecommunications

International Journal of Electronics and Telecommunications

High-Efficient Video Transmission for HDTV Broadcasting

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