Efficient two-level reverse converters for the four-moduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1}

Daghlavi, Mohammad Obeidi; Noorimehr, Mohammad Reza; Esmaeildoust, Mohammad

doi:10.1007/s10470-020-01749-z

Cited by 4 publications

(4 citation statements)

References 22 publications

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“…Hereby utilizing the Even Multiple Storage (EMS) scheme the size of the LUT-based multiplier is reduced by half which reduces the path delay and optimizes the computational complexity overhead in FIR design. In [23] memory-efficient ROM-free reverse converters design is proposed for the different sizes of moduli set to perform highspeed arithmetic with highly balanced modulus and appropriate adder units. The memory-less RNS offers significant energy efficiency with some notable path delay accumulation due to dynamic post computation.…”

Section: Related Workmentioning

confidence: 99%

Low Power RNS System Using Lut Decomposition and FSM Based Post Computation for Eeg Signal Classification

2024

Preprint

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In this paper, memory optimization and architectural level modifications are introduced for low power realization of the Residue Number System(RNS) with improved flexibility for EEG signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance FIR filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed LUT model which can produce the results without using any post accumulation process. The proposed RNS design makes use of inherent parallelism among residue channels and resources available of FPGA devices, the reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is formulated to design pre-computed reverse converters for different moduli sets and implemented based on FPGA as target devices. As a result, the proposed LUT-based direct computation-based post accumulation technique for RNS-based multiplication offers high-performance FIR filter architecture which can also allow configuring the elements for different frequency responses. Experimental results show the superior performance of decomposing LUT-based direct reverse conversion over all other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations.

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Section: Related Workmentioning

confidence: 99%

Low Power RNS System Using Lut Decomposition and FSM Based Post Computation for Eeg Signal Classification

2024

Preprint

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“…( 21) is implemented by three n-bit CSA and one n-bit carry propagate adder. It should be noted that some full adders (FAs) in these CSAs can be replaced with the couple gates of XOR/AND or XNOR/OR due to some stable values 0 or 1, respectively [51][52]. Table 1 displays the hardware details and delay of each ingredient for the first level design of the proposed reverse converter.…”

Section: Proposed Reverse Convertermentioning

confidence: 99%

“…Critical path delay estimation of various reverse converters [46] dCSA(3)+dCPAm(2n)+dCSA( 4)+dCPAm(n+1)+dCSA( )+dCPAm(n-1)+dCSA( 3)+dADD(4n) [47] dCSA (3) [52], (10n+1) dFA in addition to delays of two CSA trees with (n-2) and n inputs will be resulted. The second design structure is the same as DC1 with one extra modulo (2 n-1 -1) adder in critical path and the number of inputs of the CSA tree 1 is reduced to (n-2)/2.…”

Section: Table 3 Delay Estimation For Various Five Moduli Set Reverse...mentioning

confidence: 99%

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

Alvani

2024

EATP

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Introduction:This paper proposes two new reverse converters for balanced and wellformed five-moduli set {2 n +1, 2 n-1 -1, 2 n , 2 n+1 -1, 2 n -1}. The converters are planned in a twolevel architecture while appreciating adder base structures without utilizing any ROM, which results in an efficient implementation in VLSI circuits. Materials and Methods: To design both levels of the proposed reverse converters, Mixed-Radix Conversation (MRC) algorithm is employed. Results and Discussion: Unit gate delay and area estimation demonstrate the proposed reverse converter (DC1) is faster than other alternatives, the similar five moduli reverse converter, under distinctive dynamic ranges while the second design (DC2) requires less hardware cost. Conclusion:The synthesis results on Xilinx Virtex-7 FPGA illustrate that, comparing to the latest five moduli set reverse converters, the proposed converter (DC1) has achieved 11%, 12% and 11% improvement in speed for n = 12, 16 and 20, respectively.

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“…The Chinese remainder theorem states that if we know the remainder of the Euclidean division of an integer n by several integers, we can uniquely determine the remainder of the division of n by the product of these integers, provided that the divisors are prime to each other [32][33][34][35]. CRT algorithm is used to convert from RNS to the binary system [36][37][38].…”

Section: Chinese Remainder Theorem (Crt)mentioning

confidence: 99%

An efficient image cryptosystem based on the residue number system and hybrid chaotic maps

Kari¹,

Ghomian

2023

Preprint

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This paper presents a new method for encrypting gray-scale digital images. The proposed method uses a combination of the residue number system and chaotic maps to avoid the complexities of high-dimensional chaotic maps and improve the security of encryption and processing speed. In this method, the image pixel coordinates confusion operation is performed by Arnold's cat map, and the pixel content diffusion step is performed in two phases. In the first phase, the contents of the image pixels are converted to the introduced {(r-1)a, rb, (r + 1)c} residue number system and stored in a matrix. At the same time, a chaotic system produces a combination of Sinusoidal and Logistic maps of chaotic sequences, and after quantization, they are converted into the introduced residue number system and stored in another matrix of the same size. In the second phase of diffusion, XOR operation is performed between these two matrices. The implementation results show that the use of the residue number system, in addition to improving the evaluation parameters, improves the processing time, and the average processing time for encryption is 0.15 seconds. Also, the uniform histogram, the entropy of about 8, and the correlation coefficient close to 0 of the encrypted images all demonstrate the high security of the proposed method.

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Efficient two-level reverse converters for the four-moduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1}

Cited by 4 publications

References 22 publications

Low Power RNS System Using Lut Decomposition and FSM Based Post Computation for Eeg Signal Classification

Low Power RNS System Using Lut Decomposition and FSM Based Post Computation for Eeg Signal Classification

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

An efficient image cryptosystem based on the residue number system and hybrid chaotic maps

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