2014
DOI: 10.1049/iet-cdt.2013.0077
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Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits

Abstract: This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable … Show more

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