Efficient statistical analysis of read timing failures in SRAM circuits

Abstract

A system-level statistical analysis methodology is described that captures the impact of inter-and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size.

Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations

“…When statistical distribution of V th variation is known, one can efficiently generate yield statistics from the transistor-level verification results. There exists serious concern of 6T-SRAM with V th variation [5], [6]. The resulting mismatch among transistors can lead to SRAM functional failures during read and write operations.…”

Multi-port FinFET SRAM design

“…In FinFET, the gate tunneling current is negligible, compared to the sub-threshold one. Read performance is evaluated in terms of read time, which is the time between the rise of word line and the time the sense amplifier can detect the voltage difference of the two bit lines [18]. We evaluate the write performance using two metrics: write time and critical pulse width.…”

Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges

“…Global search method [8] can find one point on the "yield boundary" with one-time simulation and thus save more runtime. Response surface modeling method [9] tries to model the performance as a polynomial function of all variable parameters and then evaluate the yield estimation. In addition, design centering method [10], performance modeling method [11] and other advanced techniques can also be used for parametric yield estimation.…”