Efficient solution space exploration based on segment trees in analog placement with symmetry constraints

Balasa, Florin; Maruvada, S.C.; Krishnamoorthy, Karthik

doi:10.1145/774572.774645

Cited by 19 publications

(30 citation statements)

References 11 publications

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“…In the first set of experiments, we compared our algorithm with the following works: SPs [8], segment trees [3], TCG-S [15], and SPs with dummy nodes [17]. Table V lists the names of the MCNC benchmark circuits ("Circuit"), the total areas ("Area"), and the runtimes ("Time") for the aforementioned works and our HB * -tree with area optimization alone, same as the previous works, and with simultaneous area and wire-length optimization.…”

Section: Resultsmentioning

confidence: 99%

“…Table V lists the names of the MCNC benchmark circuits ("Circuit"), the total areas ("Area"), and the runtimes ("Time") for the aforementioned works and our HB * -tree with area optimization alone, same as the previous works, and with simultaneous area and wire-length optimization. The results of the works in [3], [8], and [15] are taken from [15], and those of [17] are based on the package provided by the authors. The results show that our HB * -tree achieves average area reductions of 3%, 2%, 1%, and 2% over [3], [8], [15], and [17], respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Balasa et al derived the symmetric-feasible conditions for several popular floorplan representations including sequence pairs (SPs) [8], O-tree [9], and binary trees [10]. To explore the solution space in the symmetric-feasible binary trees, they augmented the B * -tree [11] using various data structures, including segment trees [3], [12], red-black trees [13], and deterministic skip lists [14]. Lin et al [15] also presented the symmetric-feasible conditions for the TCG-S representation.…”

Section: A Previous Workmentioning

confidence: 99%

“…Specifically, the packing complexity of the previous works [8]- [10], [15]- [17], [19] are all O(n 2 ) time while those of [3], [12]- [14] need O(n lg n) time (the work in [18] requires O(m · n lg lg n) time, which was the fastest previous work).…”

Section: B Our Contributionsmentioning

confidence: 99%

“…Failure to adequately balance thermal coupling in a differential circuit can even introduce unwanted oscillations [3]. Furthermore, the symmetric modules are preferred to be placed at closest proximity for better parasitic matching and other electrical properties.…”

mentioning

confidence: 99%

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Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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