Efficient Sequential Architecture for the AES CCM Mode in the 802.16e Standard

Ji, Jae Deok; Jung, Seok Won; Jun, Eun-A; Lim, Jongim

doi:10.1109/icinis.2009.71

Cited by 6 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are many hardware implementation approaches of AES-CCM in different design aspects e.g. AES-CCM sequential architecture [10] or interleave architecture [11], [12], [13] and [14] which uses one AES encryption core for both CTR and CBC mode for resources saving. Hence, its throughput is low.…”

Section: Previous Related Workmentioning

confidence: 99%

High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network

Nguyen¹,

Lanante²,

Ochi

2013

JOACE

View full text Add to dashboard Cite

This paper presentsa new architecture andASICimplementation of high throughput of Counter with Cipher Block Chaining-Message Authentication Code(CCM) for robust security network such as gigabit wireless IEEE 802.11ac in case considering trade-off between throughput and resource saving. We propose a new architecture of AES-CCM core adopted in parallel which utilizes two separated AES forward cipher cores for MIC calculation in Counter (CTR) Mode and encryption or decryption data in Cipher Block Chaining (CBC) Mode. The implementation of AES-CCM core in Synopsys CMOS SAED90nm process achieves2.69Gbps of throughput at 264MHz clock frequency.The proposed architecture of AES-CCM corereduces latencyby one AES cycle in comparison with conventional architectures. In addition,the AES-CCM core supports bothgeneration-encapsulation and decryption-verifica-tionprocess with symmetrical data processing routine. We also introduce an implementation of reordering AES transformation method comes along with composite Sbox in order to gain maximal period of the composition and saving resources compared to original AES algorithm implementation.  .

show abstract

Section: Previous Related Workmentioning

confidence: 99%

High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network

Nguyen¹,

Lanante²,

Ochi

2013

JOACE

View full text Add to dashboard Cite

show abstract

“…In our previous related work [5], the location of SubBytes dividing point was not optimal point and SubBytes logic in the key scheduling block used the SBOX look-up table. In this paper, in order to improve sequential AES CCM architecture, we have searched the optimal point achieving maximal throughput per a slice for a targeting device.…”

Section: Introductionmentioning

confidence: 99%

Efficient Sequential Architecture of AES CCM for the IEEE 802.16e

Ji¹,

Jung

Lim³

2012

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

SUMMARYIn this paper, we propose efficient sequential AES CCM architecture for the IEEE 802.16e. In the proposed architecture, only one AES encryption core is used and the operation of the CTR and the CBC-MAC is processed concurrently within one round. With this design approach, we can design sequential AES CCM architecture having 570 Mbps@102.4 MHz throughput and 1,397 slices at a Spartan3 3s5000 device.

show abstract

Efficient Pipelined Multistream AES CCMP Architecture for Wireless LAN

Rha

Choi

2012

2012 International Conference on Information Science and Applications

View full text Add to dashboard Cite

Efficient Sequential Architecture for the AES CCM Mode in the 802.16e Standard

Cited by 6 publications

References 6 publications

High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network

High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network

Efficient Sequential Architecture of AES CCM for the IEEE 802.16e

Efficient Pipelined Multistream AES CCMP Architecture for Wireless LAN

Contact Info

Product

Resources

About