Efficient SAT-based Boolean matching for FPGA technology mapping

Abstract

Abstract-Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology mapping has the potential of providing unique optimizations unavailable through other techniques. This paper proposes a Boolean matching approach for FPGA technology mapping targeting networks of PLBs. To overcome the demanding memory requirements of previous approaches, the Boolean matching problem is formulated as a Boolean Satisfiability (SAT) problem. Since the SAT formulation provides a trade-off between space and time, the primary objective is to increase the efficiency of the SAT-based approach. To do this, the original SAT problem is decomposed into two easier SAT problems. To reduce the problem search space, a theorem is introduced to allow conflict clauses to be shared across problems and extra constraints are generated. Experiments demonstrate a 340% run time improvement and 27% more success in mapping than previous SAT-based approaches.

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

“…Improve the SAT solving part by using a better SAT solver (like MiniSAT [8]) and by doing some preprocessing of the SAT problems. This could be a combination of the work presented in [17] and a SAT preprocessor like the one supplied with MiniSAT.…”

“…The number of distinct combinations to a single LUT is n choose k ( ) not the combinations produced by the SAT-BM-M formulation. A similar improvement for a different architecture was presented in [17]. The way we reduce the number of combinations by k!…”

“…This data suggests that this method can easily test very large functions as long as their fullimplicant representation is compact. On the other hand, when the number of inputs to the LUT grows very large, we would recommend using the methods in [11] and [17] instead of the one presented in this paper. …”

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

“…9,10 Ideas in the same context as our proposed approach, trying to use Boolean matching techniques for the optimization of the mapping process have been presented. Some proposed a Boolean matching technique for mapping on networks of programmable logic blocks (PLBs), 11 expressing it as a Boolean satis¯ability problem; however their approach remained algorithmic since they did not speci¯cally exploit the available architecture while performing the Boolean matching. Others tried to add to the algorithmic power some intelligence derived from observed architectural symmetries of the structure used 12 ; however, this approach did not venture into con¯guring the FPGA's logic blocks in order to achieve better mappability.…”

Improving Bounds for FPGA Logic Minimization

“…Safarpour et al. [8] decompose the resulting SAT problem into two easier problems to increase efficiency. Cong et al [9] derive their SAT formulation from the implicant rather than the minterm representation of the problem, creating a smaller problem which can be solved faster and cover more target problems.…”